Lyra 24S

Introduction

The Lyra 24S is a secure, high-performance wireless module optimized for the needs of battery and line-powered IoT devices running on Bluetooth networks.

Based on the Series 2 EFR32BG24 SoC, it enables Bluetooth® Low Energy connectivity, delivering exceptional RF performance and energy efficiency, industry-leading Se- cure Vault® technology, and future-proofing capabilities.

The Lyra 24S is a complete System in Package solution offered with robust and fully upgradeable software stacks, global regulatory certifications, advanced development and debugging tools, and documentation that simplifies and minimizes the development cycle of your end-product, helping to accelerate its time-to-market.

Overview

This document describes key hardware aspects of the Lyra 24S. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the Lyra 24S, visit:

https://www.ezurio.com/lyra24-series

This datasheet is subject to change. Please contact Ezurio for further information.

Application Areas

• Smart Home Devices
• Lighting
• Gateways and Digital Assistants
• Building Automation and Security

Features & Benefits

The Lyra 24 device features and benefits are described below.

• Bluetooth Low Energy 5.4
• Bluetooth Mesh connectivity
• Built-in antenna or RF pin
• Up to 10 dBm TX output power (see Maximum Regulatory Certified RF TX Power per Country)
• -97 dBm BLE 1M RX sensitivity
• 32-bit ARM® Cortex®-M33 core running up to 78 MHz
• 1536/256 kB of Flash/RAM memory
• Vault High or Vault Mid security
• Rich set of analog and digital peripherals
• 32 GPIO pins
• -40 to 105 °C
• 7mm x 7mm x 1.18mm

Specification Summary

Processor / SoC / Chipset

Bluetooth

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Architecture

Block Diagrams

The Lyra 24S module is a highly integrated, high-performance system in package with all the hardware components needed to enable 2.4 GHz wireless connectivity and support robust networking capabilities via multiple wireless protocols.

Built around the EFR32BG24 Wireless SoC, the Lyra 24S includes a built-in antenna, an RF matching network (optimized for transmit power efficiency), supply decoupling and filtering components, an LC tank for DC-DC conversion, a 39 MHz reference crystal, and an RF shield. Also, it supports the use of an external 32 kHz crystal as a low frequency reference signal via GPIO pins for use cases demanding maximum energy efficiency.

For designs where an external antenna solution may be beneficial, a module variant with a 50 Ω-matched RF pin instead of the built-in antenna is available.

A simplified internal schematic for the Lyra 24S module is shown below.

EFR32BG24 SoC

The EFR32BG24 SoC features a 32-bit ARM Cortex M33 core, a 2.4 GHz high-performance radio, 1536 kB of Flash memory, 256 kB of RAM, a dedicated core for security, a rich set of MCU peripherals, and various clock management and serial interfacing options. See the EFR32xG24 Reference Manual for details.

Integrated Antenna

Lyra 24S modules come with two antenna solution variants: a built-in integral ground loop type antenna realized by a PCB trace design, or a 50Ω-matched RF pin to support an external antenna. Typical performance characteristics for the built-in antenna are detailed in the table below. See Antenna Characteristics and External Antenna Integration with the Lyra 24S Module 453-00170 for other relevant details.

Antenna efficiency, gain, and radiation pattern are dependent on the application PCB layout and mechanical design. Antenna specification is based on the assumption that the host board design guidelines in section are followed.

External Antenna

Lyra 24S module can be used with external antennas (certified by Ezurio) and requires a RF 50 Ohm track (Ground Coplanar Waveguide) to be designed to run from Lyra 24S module 2G4IO (pin 6) to an RF antenna connector (IPEX MHF 4) on the host PCB. The 50Ohm RF track design and length MUST be copied as defined in section Lyra 24S Module 50 Ohms RF Track Design for Connecting External Antenna with the Lyra 24S.

The list of supported external antennas (certified by Ezurio) are listed in section External Antenna Integration with the Lyra 24S Module

Power Supply

The Lyra 24S requires a primary supply (VDD) and IO supply (VDDIO) voltage to operate. All necessary decoupling, filtering and DC-DC-related components are included in the module.

General Purpose Input/Output (GPIO)

The Lyra 24S has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts.

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon which internal peripherals could once again drive those pads.

A few GPIOs also have EM4 wake functionality. These pins are listed in Alternate Pin Functions.

Security

Lyra 24S modules support one of two levels in the Security Portfolio offered by Silicon Labs: Secure Vault Mid or Secure Vault High.   Lyra 24S modules support Secure Vault High.

Secure Vault is a collection of technologies that deliver state-of-the-art security and upgradability features to protect and future proof IoT devices against costly threats, attacks, and tampering. A dedicated security CPU enables the Secure Vault functions and isolates cryptographic functions and data from the Cortex-M33 core.  Lyra 24S support Secure Vault High.

Secure Vault Features

Secure Boot with Root of Trust and Secure Loader (RTSL)

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over The Air updates. For more information about this feature, see Silicon Labs’ AN1218: Series 2 Secure Boot with RTSL.

Cryptographic Accelerator

The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to protect keys.

It supports AES encryption and decryption with 128/192/256-bit keys, ChaCha20 encryption, and Elliptic Curve Cryptography (ECC) to support public key operations, and hashes.

Supported block cipher modes of operation for AES include:

• ECB (Electronic Code Book)
• CTR (Counter Mode)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• GCM (Galois Counter Mode)
• CCM (Counter with CBC-MAC)
• CBC-MAC (Cipher Block Chaining Message Authentication Code)
• GMAC (Galois Message Authentication Code)

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and Technology) recommended curves including P-192, P-256, P-384, and P-521 for ECDH (Elliptic Curve Diffie-Hellman) key derivation, and ECDSA (Elliptic Curve Digital Signature Algorithm) sign and verify operations. Also supported is the non-NIST Curve25519 for ECDH and Ed25519 for EdDSA (Edwards-curve Digital Signature Algorithm) sign and verify operations.

Secure Vault also supports ECJ-PAKE (Elliptic Curve variant of Password Authenticated Key Exchange by Juggling) and PBKDF2 (Password-Based Key Derivation Function 2).

Supported hashes include SHA-1, SHA-2/256/384/512 and Poly1305.

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.

True Random Number Generator

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online health tests required for NIST SP800-90C.

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.

Secure Debug with Lock/Unlock

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.

In addition, Secure Vault High also provides a secure debug unlock function that allows authenticated access based on public key cryptography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-user data.

For more information about this feature, see Silicon Labs’ AN1190: Series 2 Secure Debug.

DPA Countermeasures

The AES and ECC accelerators have Differential Power Analysis (DPA) countermeasures support. This makes it very expensive from a time and effort standpoint to use DPA to recover secret keys.

Secure Key Management with PUF

Key material in Secure Vault High products is protected by "key wrapping" with a standardized symmetric encryption mechanism. This method has the advantage of protecting a virtually unlimited number of keys, limited only by the storage that is accessible by the Cortex-M33, which includes off-chip storage as well. The symmetric key used for this wrapping and unwrapping must be highly secure because it can expose all other key materials in the system. The Secure Vault Key Management system uses a Physically Unclonable Function (PUF) to generate a persistent device-unique seed key on power up to dynamically generate this critical wrapping/unwrapping key which is only visible to the AES encryption engine and is not retained when the device loses power.

Anti-Tamper

Secure Vault High devices provide internal tamper protection which monitors parameters such as voltage, temperature, and electro- magnetic pulses as well as detecting tamper of the security sub-system itself. Additionally, 8 external configurable tamper pins support external tamper sources, such as enclosure tamper switches.

For each tamper event, the user is able to select the severity of the tamper response ranging from an interrupt, to a reset, to destroying the PUF reconstruction data which will make all protected key materials un-recoverable and effectively render the device inoperable. The tamper system also has an internal resettable event counter with programmable trigger threshold and refresh periods to mitigate false positive tamper events.

For more information about this feature, see Silicon Labs’ AN1247: Anti-Tamper Protection Configuration and Use.

Secure Attestation

Secure Vault High products support Secure Attestation, which begins with a secure identity that is created during the Silicon Labs manufacturing process. During device production, each device generates its own public/private keypair and securely stores the wrapped private key into immutable OTP memory and this key never leaves the device. The corresponding public key is extracted from the device and inserted into a binary DER-encoded X.509 device certificate, which is signed into a Silicon Labs CA chain and then programmed back into the chip into an immutable OTP memory.

The secure identity can be used to authenticate the chip at any time in the life of the product. The production certification chain can be requested remotely from the product. This certification chain can be used to verify that the device was authentically produced by Silicon Labs. The device unique public key is also bound to the device certificate in the certification chain. A challenge can be sent to the chip at any point in time to be signed by the device private key. The public key in the device certificate can then be used to verify the challenge response, proving that the device has access to the securely stored private key, which prevents counterfeit products or impersonation attacks.

For more information about this feature, see Silicon Labs’ AN1268: Authenticating Silicon Labs Devices Using Device Certificates.

Pin-Out / Package Layout

For GPIO pin to peripheral assignment in AT firmware, see User Guide – AT Interface Application – Lyra 24 Series.

The next table shows the Lyra 24S pinout and general descriptions for each pin. Refer to Alternate Pin Functions, Analog Peripheral Connectivity, and Digital Peripheral Connectivity for details on functions and peripherals supported by each GPIO pin.

Alternate Pin Functions

Some GPIOs support alternate functions like debugging, wake-up from EM4, external low frequency crystal access, etc. The following table shows both which module pins have alternate capabilities and the functions they support. Refer to the SoCs reference manual for more details.

Analog Peripheral Connectivity

Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are available on each GPIO port. When a differential connection is being used, positive inputs are restricted to the EVEN pins and negative inputs are restricted to the ODD pins. When a single ended connection is being used positive input is available on all pins. See the SoC's Reference Manual for more details on the ABUS and analog peripherals.

Digital Peripheral Connectivity

Many digital resources are routable and can be connected to numerous GPIOs. The table below indicates which peripherals are available on each GPIO port.

Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T_A=25 °C and VDD = VDDIO = 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Absolute Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics

RF Transmitter General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. T_A = 25°C.

RF Receiver General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. T_A = 25°C.

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. T_A = 25°C.

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. TA = 25°C.

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. T_A = 25°C.

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. RF center frequency 2.45 GHz. T_A = 25°C.

High-Frequency Crystal

Low-Frequency Crystal Oscillator

Precision Low Frequency RC Oscillator (LFRCO)

GPIO Pins

Microcontroller Peripherals

The set of peripherals available in Lyra 24S modules includes:

• 12-bit 1 Msps ADC
• Analog Comparators
• 16-bit and 32-bit Timers/Counters
• 24-bit Low Energy Timer for waveform generation
• 32-bit Real Time Counter
• USART (UART/SPI/SmartCards/IrDA/I2S)
• I2C peripheral interfaces
• 12 Channel Peripheral Reflex System

Details on their electrical performance can be found in the relevant portions of Section 4 of the EFR32BG24 SoC datasheet.

To learn which GPIO ports provide access to every peripheral, consult Analog Peripheral Connectivity and Digital Peripheral Connectivity.

Current Consumption

MCU Current Consumption at 3.0V

Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. Voltage scaling level = VSCALE1. T_A = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T_A = 25 °C.

Radio Current Consumption with 3.0 V Supply

RF current consumption measured with MCU in EM1 and all MCU peripherals disabled. Unless otherwise indicated, typical conditions are: VDD = VDDIO = 3.0 V, DC-DC in regulation. T_A = 25 °C.

Integration Guidelines

Antenna Characteristics

Typical Lyra 24S radiation patterns for the built-in antenna under optimal operating conditions are plotted in the figures that follow. Antenna gain and radiation patterns have a strong dependence on the size and shape of the application PCB the module is mounted on, as well as on the proximity of any mechanical design to the antenna.

Impact of Human Body and Other Materials in Close Proximity

Placing the module in contact with or very close to the human body will negatively impact antenna efficiency and reduce range.

Avoid placing plastic or any other dielectric material near the antenna. Conformal coating and other thin dielectric layers are acceptable directly on top of the antenna region, but this will also negatively impact antenna efficiency and reduce range.

Any metallic objects near the antenna will prevent the antenna from radiating freely. The minimum recommended distance of metallic and/or conductive objects is 10 mm in any direction from the antenna except in the directions of the application PCB ground planes.

Circuit (Overview and Checklist)

PCB Layout

PCB Layout on Host PCB - General

For optimal performance of the Lyra 24S the following guidelines are recommended:

• Place the module 1.50 mm from the edge of the copper “keep-in” area at the middle of the long edge of the application PCB, as illustrated in Recommended Layout for Lyra 24S (Integrated Antenna) below.
• Copy the exact design from TOP Layer Antenna Layout with Coordinates below with the values for coordinates A to L given in Antenna Polygon Coordinates table below, Referenced to Center of Lyra 24S.
• Make a cutout in all lower layers aligned with the right edge and the bottom edge of the integral loop antenna as indicated by the red box in Antenna Clearance in Inner and Bottom Layers below.
• Connect all ground pads directly to a solid ground plane in the top layer.
• Connect 2G4IO to ANT_IN through a 0-ohm resistor.
• The 0-ohm gives the ability to test conducted and to evaluate the antenna impedance in the design.
• Place ground vias as close to the ground pads of the Lyra 24S as possible.
• Place ground vias along the antenna loop right and bottom side.
• Place ground vias along the edges of the application board.
• Do not place plastic or any other dielectric material in contact with the antenna.
• A minimum clearance of 0.5 mm is advised.
• Solder mask, conformal coating and other thin dielectric layers are acceptable directly on top of the antenna region.
• Proper module placement and electrical connection should be ensured by measuring radiated output power from antenna.
• Impedance of the antenna can be verified by measuring S11 at ANT_IN pin that is corresponding antenna specification.
• With an external antenna, use a 50Ω trace to connect RF signal to the antenna, as it is illustrated in section  Lyra 24S Module 50 Ohms RF Track Design for Connecting External Antenna with the Lyra 24S.

Antenna Polygon Coordinates, Referenced to Center of Lyra 24S

Tolerance for the coordinates is +/- 0.05 mm.

Best Design Practices

• The design of a good RF system relies on thoughtful placement and routing of the RF signals. The following guidelines are recommended:
• Place the Lyra 24S and antenna close to the center of the longest edge of the application board.
• Do not place any circuitry between the board edge and the antenna.
• Make sure to tie all GND planes in the application board together with as many vias as can be fitted.
• Generally, ground planes are recommended in all areas of the application board except in the antenna keep-out area shown in the previous diagram.
• Open-ended stubs of copper in the outer layer ground planes must be removed if they are more than 5 mm long to avoid radiation of spurious emissions.
• The width of the GND plane to the sides of the Lyra 24S will impact the efficiency of the on-board integral loop antenna.
• To achieve optimal performance, a GND plane width of 55 mm is recommended as seen below.

• See Antenna Radiation and Efficiency for Lyra 24S Integrated Antenna for reference. The below illustrates layout scenarios that will lead to severely degraded RF performance for the application board. Antenna Keep-Out on Host PCB.

Radio Performance vs. Carrier Board Size

As with most applications, the carrier board size is determined by the overall form factor or size of the additional circuitry. The recommended carrier board width of 55 mm is thus not always possible in the end-application. If another form factor is required, the antenna performance of the integrated antenna will likely be compromised, but it may still be sufficiently good for providing the required link quality and range of the end-application. As can be seen below, the best performance is achieved for a carrier board size of 55 mm x 30 mm, with relatively constant performance for larger boards and rapidly declining performance for smaller boards.

External Antenna Integration

Lyra 24S Module 50 Ohms RF Track Design for Connecting External Antenna with the Lyra 24

Lyra 24S module can be used with external antennas (certified by Ezurio), and requires a 50 Ohm RF trace (GCPW, that Grounded Coplanar Waveguide) to be designed to run from Lyra 24S module 2G4IO (pin6) to a RF antenna connector (IPEX MHF4) on host PCB.  The 50 Ohms RF track design and length MUST be copied (as specified in this section).  Lyra 24SP module GND pin7 used to support GCPW 50Ohm RF trace.

Lyra 24S for External antenna connection host PCB 50-Ohm RF trace schematic with MHF4 RF connector

Lyra 24S External antenna connection	Lyra 24S Internal antenna connection
Fit IPEX MHF4 RF connector (20449-001E), J3. Fit 0R resistor (position R940 in below SCH) between Lyra 24S module pin6 (2G4IO) and IPEX MHF4 RF connector (20449-001E). Leave Lyra 24S module pin5 (ANT_IN) open circuited.	Fit 0R resistor (position R939 in below SCH) between Lyra 24S module pin6 (2G4IO) and pin5 (ANT_IN). Do not Fit R940 and J3 (positions in below SCH). Lyra 24S pin5 (ANT_IN internal antenna PCB layout MUST be followed.

Layer1 (RF Track and RF GND)

Layer2 (RF GND)

Checklist for PCB:

• MUST use a 50-Ohm RF trace (GCPW, that is Grounded Coplanar Waveguide) from 2F4IO (pin6) of the Lyra 24S module (453-00170) to RF antenna connector (IPEX MHF4 Receptable (MPN: 20449-001E)) on host PCB.
• To ensure regulatory compliance, MUST follow exactly the following considerations for 50-Ohms RF trace design and test verification:

External Antenna Integration with the Lyra 24S Module 453-00170

Please refer to the Lyra 24S Regulatory Information Guide for details on using Lyra 24S module with external antennas in each regulatory region. The Lyra 24S has been designed to operate with the below external antennas (with a maximum gain of 2.0dBi). The required antenna impedance is 50 ohms. See below. External antennas improve radiation efficiency.

Host Platform Implementation Details

Network Co-Processor (NCP) Application with UART Host

The Lyra 24S can be controlled via the UART interface as a peripheral to an external host processor. Typical power supply, programming/debug interface, and host interface connections are shown in the figure below.  For more details, see AN958: Debugging and Programming Interfaces for Custom Designs.

SoC Application

The Lyra 24S can be used in a stand-alone SoC configuration without an external host processor. Typical power supply and programming/debug interface connections are shown in the figure below.  For more details, see AN958: Debugging and Programming Interfaces for Custom Designs.

Boot

The BOOT pin is used to determine when execution of the bootloader is required. Upon reset, execution of the bootloader begins. The state of the BOOT pin is read immediately upon start-up of the bootloader. If LOW, execution of the bootloader continues, facilitating firmware update via the UART. If the BOOT pin is HIGH, the bootloader will stop execution and pass control to the main application firmware.

Reset

The Lyra 24S can be reset by pulling the RESET line low, by the internal watchdog timer, or by software command. The reset state does not provide power saving functionality and it is not recommended as a means to conserve power.

Debug

See Silicon Labs’ AN958: Debugging and Programming Interfaces for Custom Designs.

The Lyra 24S supports hardware debugging via 4-pin JTAG or 2-pin serial-wire debug (SWD) interfaces. It is recommended to expose the debug pins in your own hardware design for firmware update and debug purposes. The table below lists the required pins for JTAG and SWD debug interfacing, which are also presented in Alternate Pin Functions.

If JTAG interfacing is enabled, the module must be power cycled to return to a SWD debug configuration if necessary.

Packet Trace Interface (PTI)

The Lyra 24S integrates a true PHY-level packet trace interface (PTI) peripheral that can capture packets non-intrusively to monitor and log device and network traffic without burdening processing resources in the module's SoC. The PTI generates two output signals that can serve as a powerful debugging tool, especially in conjunction with other hardware and software development tools available from Silicon Labs. The PTI_DATA and PTI_FRAME signals can be accessed through any GPIO on ports C and D (see FRC.DOUT and FRC.DFRAME peripheral resources in Pin Out / Package Layout).

WL_DEV_WAKE Mapping

Application Note for Surface Mount Modules

Shipping and Labeling

PCB Land Pattern

Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling.

Package Marking

Tray and Reel

Lyra 24S modules are delivered to the customer in Tray or reel. Find the packaging dimensions below. All dimensions are given in mm unless otherwise indicated.

Recommended Stencil Aperture

Reflow Parameters/ Soldering

Reflow for lead Free Solder Paste

Optimal solder reflow profile depends on solder paste properties and should be optimized as part of an overall process development.

• It is important to provide a solder reflow profile that matches the solder paste supplier's recommendations.
• Temperature ranges beyond that of the solder paste supplier's recommendation could result in poor solderability.
• All solder paste suppliers recommend an ideal reflow profile to give the best solderability.

Recommended Reflow Profile for lead Free Solder Paste

Miscellaneous

Cleaning

In general, cleaning the populated modules is strongly discouraged. Residuals under the module cannot be easily removed with any cleaning process.

• Cleaning with water can lead to capillary effects where water is absorbed into the gap between the host board and the module. The combination of soldering flux residuals and encapsulated water could lead to short circuits between neighboring pads. Water could also damage any stickers or labels.

• Cleaning with alcohol or a similar organic solvent will likely flood soldering flux residuals into the RF shield, which is not accessible for post-washing inspection. The solvent could also damage any stickers or labels.

• Ultrasonic cleaning could damage the module permanently.

Rework

The Lyra 24P module can be unsoldered from the host board if the Moisture Sensitivity Level (MSL) requirements are met as described in this datasheet.

Never attempt a rework on the module itself, i.e. replacing individual components. Such actions terminate warranty coverage.

Environmental and Reliability

Environmental Requirements

Handling Requirements

The Lyra 24P module contain a highly sensitive electronic circuitry. Handling without proper ESD protection may damage the module permanently.

Moisture Sensitivity Level (MSL)

Per J-STD-020, devices rated as MSL 4 and not stored in a sealed bag with desiccant pack should be baked prior to use.

Devices are packaged in a Moisture Barrier Bag with a desiccant pack and Humidity Indicator Card (HIC). Devices that will be subjected to reflow should reference the HIC and J-STD-033 to determine if baking is required.

If baking is required, refer to J-STD-033 for bake procedure.

Required Storage Conditions

Per J-STD-033, the shelf life of devices in a Moisture Barrier Bag is 12 months at <40C and <90% room humidity (RH).

Do not store in salty air or in an environment with a high concentration of corrosive gas, such as Cl2, H2S, NH3, SO2, or NOX. Do not store in direct sunlight.

The product should not be subject to excessive mechanical shock.

Repeated Reflow Soldering

Only a single reflow soldering process is encouraged for host boards.

Reliability Tests

Climatic and Dynamic

Reliability Prediction

Reliability Prediction Approach

• Apply Telcordia SR-232 Issue 3 Parts Count calculation
• Confidence Level 90%
• Quality Level II

Regulatory, Qualification & Certifications

Regulatory Approvals

The Lyra 24S holds current certifications in the following countries:

Certified Antennas

Maximum Regulatory Certified RF TX Power per Country

For shipped AT Firmware

Ezurio AT firmware implements maximum RF TX power settings per country highlighted below.

453-00170 Lyra 24P – Bluetooth v5.4 PCB Module (10dBm) with Integrated Antenna is shipped AT firmware where the radio regulatory region “global” is set which is lowest common settings across RF TX power across certified countries. To switch to the specific radio regulatory region country of USA, Canada, Europe, UK, Australia, New Zealand, Japan and South Korea, customer can use appropriate AT command for setting the radio regulatory region per country.

For Customers C Code Development -

Customers developing with C Code – Full software development with Silicon Labs SDK and Toolchain, MUST implement the maximum RF TX power settings per country and other parameters mentioned in this section.

AFH Firmware Module Description

See Silabs AFH firmware module (in Silabs BLE stack) operation description https://docs.silabs.com/bluetooth/5.0/general/system-and-performance/adaptive-frequency-hopping

This was enabled for CE Adaptivity requirements (since Lyra 24S declared as Adaptive for CE), so left enabled for all certified countries.

Europe (CE), UK (UKCA), Australia (RCM, New Zealand (RCM) Radio RF TX power Table

USA (FCC), Canada (ISED) Radio RF TX power Table

Japan (MIC) Radio RF TX Power Table

South Korea Radio RF TX Power Table

Global (Lowest Common Across Certified Countries) Radio RF TX Power Table

Bluetooth SIG Qualification

The Bluetooth Qualification Process promotes global product interoperability and reinforces the strength of the Bluetooth® brand and ecosystem to the benefit of all Bluetooth SIG members. The Bluetooth Qualification Process helps member companies ensure their products that incorporate Bluetooth technology comply with the Bluetooth Patent & Copyright License Agreement and the Bluetooth Trademark License Agreement (collectively, the Bluetooth License Agreement) and Bluetooth Specifications.

The Bluetooth Qualification Process is defined by the Qualification Program Reference Document (QPRD) v3.

To demonstrate that a product complies with the Bluetooth Specification(s), each member must for each of its products:

• Identify the product, the design included in the product, the Bluetooth Specifications that the design implements, and the features of each implemented specification
• Complete the Bluetooth Qualification Process by submitting the required documentation for the product under a user account belonging to your company

The Bluetooth Qualification Process consists of the phases shown below:

To complete the Qualification Process the company developing a Bluetooth End Product shall be a member of the Bluetooth SIG.  To start the application please use the following link: Apply for Adopter Membership

Scope

This guide is intended to provide guidance on the Bluetooth Qualification Process for End Products that reference multiple existing designs, that have not been modified, (refer to Section 3.2.2.1 of the Qualification Program Reference Document v3).

For a Product that includes a new Design created by combining two or more unmodified designs that have DNs or QDIDs into one of the permitted combinations in Table 3.1 of the QPRDv3, a Member must also provide the following information:

• DNs or QDIDs for Designs included in the new Design
• The desired Core Configuration of the new Design (if applicable, see Table 3.1 below)
• The active TCRL Package version used for checking the applicable Core Configuration (including transport compatibility) and evaluating test requirements

Any included Design must not implement any Layers using withdrawn specification(s).

When creating a new Design using Option 2a, the Inter-Layer Dependency (ILD) between Layers included in the Design will be checked based on the latest TCRL Package version used among the included Designs.

For the purposes of this document, it is assumed that the member is combining unmodified Core-Controller Configuration and Core-Host Configuration designs, to complete a Core-Complete Configuration.

Qualification Steps When Referencing a single existing design, (unmodified) – Option 1 in the QPRDv3

For this qualification, follow these steps:

1. To start a listing, go to: https://qualification.bluetooth.com/

2. Select Start the Bluetooth Qualification Process.

3. Product Details to be entered:

• Project Name (this can be the product name or the Bluetooth Design name).
• Product Description
• Model Number
• Product Publication Date (the product publication date may not be later than 90 days after submission)
• Product Website (optional)
• Internal Visibility (this will define if the product will be visible to other users prior to publication)
• If you have multiple End Products to list then you can select ‘Import Multiple Products’, firstly downloading and completing the template, then by ‘Upload Product List’.  This will populate Qualification Workspace with all your products.

4. Specify the Design:

• Do you include any existing Design(s) in your Product? Answer Yes, I do.
• Enter the single DN or QDID used in your, (for Option 1 only one DN or QDID can be referenced)
• Once the DN or QDID is selected it will appear on the left-hand side, indicating the layers covered by the design.
• Select ‘I’m finished entering DN’s
• What do you want to do next? Answer, ‘Use this Design without Modification’
• Save and go to Product Qualification Fee

5. Product Qualification Fee:

• It’s important to make sure a Prepaid Product Qualification fee is available as it is required at this stage to complete the Qualification Process.
• Prepaid Product Qualification Fee’s will appear in the available list so select one for the listing.
• If one is not available select ‘Pay Product Qualification Fee’, payment can be done immediately via credit card, or you can pay via Invoice.  Payment via credit will release the number immediately, if paying via invoice the number will not be released until the invoice is paid.
• Once you have selected the Prepaid Qualification Fee, select ‘Save and go to Submission’

6. Submission:

• Some automatic checks occur to ensure all submission requirements are complete.
• To complete the listing any errors must be corrected
• Once you have confirmed all design information is correct, tick all of the three check boxes and add your name to the signature page.
• Now select ‘Complete the Submission’.
• You will be asked a final time to confirm you want to proceed with the submission, select ‘Complete the Submission’.
• Qualification Workspace will confirm the submission has been submitted.  The Bluetooth SIG will email confirmation once the submission has been accepted, (normally this takes 1 working day).

7. Download Product and Design Details:

• You can now download a copy of the confirmed listing from the design listing page and save a copy in your Compliance Folder

For further information, please refer to the following webpage:

https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/

Example Design Combinations

The following gives an example of a design possible under option 1:

Ezurio End Product design using Silicon Labs Component based design

Qualify More Products

If you develop further products based on the same design in the future, it is possible to add them free of charge.  The new product must not modify the existing design i.e add ICS functionality, otherwise a new design listing will be required.

To add more products to your design, select ‘Manage Submitted Products’ in the Getting Started page, Actions, Qualify More Products.  The tool will take you through the updating process.

Ordering Information

Lyra 24S series modules operate in the 2.4 GHz ISM frequency band (BLE range: 2402-2480MHz).

The maximum RF TX power allowed by different regional regulatory authorities may differ from the maximum output power a module can produce. End-product manufacturers must then verify that the module is configured to meet the regulatory limits for each region in accordance with the local rules and the formal certification test reports.

See section Maximum Regulatory Certified RF TX Power per Country.

Lyra 24S modules are pre-programmed with Lyra 24S BGAPI UART/OTA DFU bootloader. Lyra 24S AT firmware can be loaded by the customer (via SWD interface or via boot loader (UART or OTA)).

Legacy - Revision History