Veda SL917 SoC Module

Introduction

Overview

This document describes key hardware aspects of the Veda SL917 SoC Module. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the Veda SL917, visit:

https://www.ezurio.com/veda-sl917

General Description

Ezurio’s SL917 module is our lowest power Wi-Fi 6 plus Bluetooth LE 5.4, ideal for ultra-low power IoT wireless devices using Wi-Fi®, Bluetooth, Matter, and IP networking for secure cloud connectivity. It is optimal for developing battery operated devices that need long battery life. The SL917 SoC module includes an ultra-low power Wi-Fi 6 plus Bluetooth Low Energy (LE) 5.4 wireless CPU subsystem, and an integrated micro-controller (MCU) application subsystem, security, peripherals and power management sub- system all in a single 16 x 21.1 x 2.3 mm package. The wireless subsystem consists of a multi-threaded Network Wireless Processor (NWP) running up to 160 MHz, baseband digital signal processing, analog front end, 2.4 GHz RF transceiver and integrated power amplifier. The application subsystem consists of an ARM® Cortex®-M4 running up to 180 MHz, embedded SRAM, FLASH, ultra-low power sensor hub, and matrix vector processor. The ARM® Cortex®-M4 is dedicated for peripheral and application-related processing, while the NWP runs the wireless and networking stacks on independent threads, thus providing a fully integrated solution that is ready for a wide range of embedded wireless IoT applications. The modules come with modular radio type approvals for various countries, including USA (FCC), Canada (IC/ISED) and Japan (MIC), and are in compliance with the relevant EN standards (including EN 300 328 v2.2.2) for the conformity with the directives and regulations in EU and UK.

This datasheet is subject to change. Please contact Ezurio for further information.

Application Areas

• Smart Home
• Security cameras
• HVAC
• Smart Sensors
• Smart Appliances
• Health and Fitness
• Pet Trackers
• Smart Cities
• Smart Meters
• Industrial Wearables
• Smart Buildings
• Asset Tracking
• Smart hospitals

Features & Benefits

The Veda SL917 SoC device features and benefits are described below.

• Wi-Fi 6 Single Band 2.4 GHz 20 MHz 1x1 stream IEEE 802.11 b/g/n/ax
• Bluetooth LE 5.4
• Single chip Matter Over Wi-Fi Solution
• ARM® Cortex® M4 Processor with FPU subsystem up to 180 MHz with rich set of Digital and Analog Peripherals.
• Wi-Fi 6 Benefits: TWT for improved efficiency and longer battery life, MU- MIMO/OFDMA for Higher Throughput, network capacity and low latency
• Best in Class Device and Wireless Security
• WLAN Tx power up to +17.5 dBm with integrated PA
• Bluetooth LE Tx power up to +17 dBm with integrated PA
• WLAN Rx sensitivity as low as -95 dBm
• Wi-Fi Standby Associated mode current: 78 μA @ 1-second listen interval
• Embedded Flash option up to 8 MB/ optional external Flash up to 16 MB
• Embedded PSRAM option up to 8 MB/ optional external PSRAM option up to 16 MB
• Ultra-low power sensor hub peripherals
• Matrix Vector Processor (MVP)
• Embedded Wi-Fi, Bluetooth LE, Matter, and networking stacks supporting wireless coexistence
• Three software-configurable MCU application memory options for sharing the RAM between the wireless, system, and application (192/256/320 KB)
• Operating temperature: -40 ºC to +85 ºC
• Operating supply range: 3.0 V - 3.63 V
• Supply voltage for GPIOs: 1.71 V to 3.63 V

Specification Summary

Processor / SoC / Chipset

Wi-Fi

Bluetooth

Radio Performance

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Functional Descriptions

System Overview

The SL917 Modules include two processors: An ARM Cortex-M4 running up to 180 MHz and a Network Wireless Processor (NWP) 4-Threaded processor running up to 160 MHz. The Cortex-M4 is dedicated for peripheral and application related processing, whereas all the networking and wireless stacks run on independent threads of the NWP. In addition, in adherence to the Secure Execution Environment architecture, the NWP subsystem also acts as the secure processing domain and takes care of secure boot, secure firmware update, and provides access to security accelerators and secure peripherals through pre-defined APIs. The bus matrices of a Cortex M4 and NWP are separate and asynchronous. Though the two processors are present in a single chip, it is ensured that the NWP Networking, Security, and Wireless subsystem is completely separated from the ARM Cortex-M4 based application subsystem. Thus, these two processors have separate power, clocks/PLLs, bus-matrices, and memory. This provides two key advantages: programming, operating and power-state independence between the two processors and enhanced security by restricting access to the NWP subsystem.

SL917 modules are based on Silicon Labs’ SiWG917M ultra-low-power, single spatial stream, 802.11 b/g/n/ax + BLE 5.4 Convergence SoC. The SL917 module provides low-cost CMOS integration of a multi-threaded MAC processor, baseband digital signal processing, analog front-end, crystal oscillator, calibration eFuse, 2.4GHz RF transceiver, integrated power amplifier, matching network, bandpass filter (BPF), and Quad-SPI Flash thus providing a fully-integrated solution for a range of hosted and embedded wireless applications. With Silicon Labs' embedded four-threaded processor and on-chip ROM and RAM, these chipsets enable integration into low cost and zero host load applications. With an integrated PMU and support for a variety of digital peripherals, SL917 modules enable very low-cost implementations for wireless hosted and embedded applications. It can be connected to a host processor through SDIO, SPI or UART interfaces. Wireless firmware upgrades and provisioning are supported.

ARM Cortex M4

The ARM Cortex-M4 is the main application processor in the SiWG917M embedded SoC. It is a high-performance 32-bit processor designed by ARM for the microcontroller market. It is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The M4 processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and Single Instruction Multiple Data (SIMD) multiplication and multiply-with- accumulate capabilities, saturating arithmetic and dedicated hardware division. The Cortex M4 microcontroller integrated into SiWG917M embedded SoC supports the following features:

• MPU (Memory Protection Unit) with 8 memory regions, FPU (Floating Point Unit), and NVIC (Nested Vectored Interrupt Controller) with 64 levels of interrupt priority
• Debug port with both JTAG as well as Serial Wire Debug (SWD) interface; comprehensive debug functionality including data matching for a watch-point generation
• To provide optimal power vs performance tradeoff, unique gear-shifting is available for the Cortex-M4 that enables optimal power consumption based on the required performance. The available power-states are Power State 4 (PS4) at up to 180 MHz, Power State 3 (PS3) at up to 90 MHz, and Power State 2 (PS2) at up to 32 MHz. More details are provided in Section 5.5.4 Power States .
• Architectural clock gates are included to minimize dynamic power dissipation.
• The Network Wireless Processor and Cortex-M4 communicate through thread to thread interrupting and memory.
• On-chip M4 SRAM of 192/256/320 KB based on the SiWG917M embedded SoC chip configuration
• 8 KB is present in the ultra-low-power (ULP) peripheral subsystem. This memory is present on the S-bus of the Cortex-M4 and is primarily used by the ULP MCU peripherals like ULP I2S, etc.
• 64 KB of ROM which hold the Cortex-M4 peripheral drivers
• 16 KB of instruction cache enabling eXecute In Place (XIP) with external quad/octal SPI Single Data Rate (SDR) flashes
• Based on the SiWG917M embedded SoC package configuration, up to 8 MB of in-package Quad Serial Peripheral Interface (QSPI) flash is available for the Cortex-M4. This flash can be shared with the NWP in common flash mode.
• eFuse of 32 bytes (available for customer applications)
• 225 Dhrystone million instructions per second (DMIPS) performance

The Cortex-M4 core includes the following core peripherals:

Nested Vectored Interrupt Controller

The NVIC is an embedded interrupt controller that supports low latency interrupt processing.

Memory Protection Unit

The memory protection unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It pro- vides up to eight different regions and an optional predefined background region. It provides fine-grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data, and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive.

The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region.

The memory types are:

• Normal: The M4 processor can re-order transactions for efficiency, or perform speculative reads.
• Device: The M4 processor preserves transaction order relative to other transactions to device or strongly-ordered memory.
• Strongly-ordered: The M4 processor preserves transaction order relative to all other transactions. The different ordering requirements for device and strongly-ordered memory mean that the memory system can buffer a write to device memory, but must not buffer a write to strongly-ordered memory.

The additional memory attributes include:

• Shareable: For a shareable memory region, the memory system provides data synchronization between bus primaries in a system with multiple bus primaries, for example, a M4 processor with a Direct Memory Access (DMA) controller. Strongly-ordered memory is always shareable. If multiple bus primaries can access a non-shareable memory region, the software must ensure data coherency between the bus primaries.
• Execute Never (XN): Means the M4 processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region.

Floating-Point Unit

The Floating-point unit (FPU) provides IEEE754-compliant operations on single-precision, 32-bit, floating-point values. It supports addition, subtraction, multiplication, division and square root.

Memory Architecture

There are on chip Read Only Memory (ROM), Random Access Memory (RAM) and off chip FLASH connectivity. Sizes of ROM/RAM/ FLASH will vary depending on the chip configuration.

Highlights:

• Unified memory architecture - software can partition the memory between code and data usage
• Multiport - RAMs support multi port access - allowing simultaneous access from different primaries (I, D, DMAs) to non overlapping regions without any cycle penalty
• ROM/RAMs are tightly coupled to the M4 processor I/D buses to reduce the latency and power
• Supports memory protection - generates trap if unintended primary accesses the memory

The Cortex-M4 processor has following memory:

• On-chip M4 SRAM of 192/256/320 KB based on the chip configuration
• 8 KB is present in the Ultra-low-power(ULP) peripheral subsystem. This memory is present on the S-bus of the Cortex-M4 and is primarily used by the ULP MCU peripherals like ULP I2S, ADC, DAC etc.
• 64 KB of ROM which holds the M4 peripheral drivers and bootloader.
• 16 KB of Instruction cache (I cache) enabling eXecute In Place (XIP) with external quad/octal SPI SDR flashes.
• Based on the package configuration up to 8 MB of "in-package" Quad SPI flash is available for the M4. This flash can be shared with the NWP in common flash mode
• eFuse of 32 bytes (available for customer applications)
• 16 KB of Data cache (D cache) enabling data fetching with PSRAM and Instruction cache (I cache) to execute code from PSRAM

• Flash Memory:

  • Based on the package configuration (OPN) up to 8 MB of "in-package" Quad SPI flash is available.

  • In addition, IC can support external flash option

    • IC has the support for 2-flash configuration

      • Common flash: Flash is common for both Cortex M4 and NWP
      • Dual Flash: Separate flash can be used for Cortex M4 and NWP

Flash Architecture

Details for Flash Architecture are explained in the Flash Memory Section of the Reference Manual.

SRAM Memory Sharing between Cortex M4 and Network Wireless Processor

A configurable SRAM feature for different processors can reduce the total on-chip memory requirement while addressing the memory requirements for different product modes.

The 91x SoC architecture allows different memory sizes allocated to the Cortex M4 and NWP processors based on the chip configuration at bootup time. The allocated memory will run on the respective processor clock. Through the efficient hardware design, memory sizes are divided and accessible by multiple processors in a single cycle using tightly coupled interfaces (TCM).

On-chip SRAM memory can be allocated to the two processors in four chunks: 352 KB, 64 KB, 64 KB, and 192 KB. The 352 KB chunk is always allocated to the NWP processor while the 192 KB chunk is always allocated to the Cortex M4. The remaining two 64 KB chunks can be allocated to either the Cortex M4 or the NWP processor. For example, if the NWP processor requires more than 352 KB, and the M4 does not need all 320 KB, an additional 64 KB or 128 KB can be allocated to the NWP.

Thus the available options are for the NWP to use 352, 416, or 480 KB SRAM, with the M4 using 320, 256, or 192 KB of SRAM, respectively.

Memory configuration between the MCU and Wireless Sub-system is shown in Possible Memory Configurations between MCU and Wireless Sub-system.

The NWP and M4 memory architecture is shown below. NWPSS is the Network Wireless Processor subsystem and M4SS is the Cortex M4 subsystem.

Advanced Peripheral Bus (APB)

• The APB is part of the AMBA 3 protocol family.
• It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
• The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface.
• The APB has unpipelined protocol.
• All signal transitions are only related to the rising edge of the clock to enable the integration of APB peripherals easily into any design flow.
• Every transfer takes at least two cycles.
• It can be used to provide access to the programmable control registers of peripheral devices.

Interconnect

The following are the buses and bridges that form the interconnect in the SL917 module. MCU refers to the Cortex-M4, and NWP refers to the Network Wireless Processor.

• High Performance (HP) MCU AHB Interconnect Matrix (ICM)
• MCU AHB-to-APB dual bridge
• MCU AHB-to-ULP MCU synchronous AHB bridge
• ULP MCU AHB ICM
• ULP MCU AHB-to-APB bridge
• MCU AHB - NWP AHB bridge
• High Performance NWP AHB ICM
• NWP AHB-to-APB dual bridge

The High Performance MCU AHB ICM is a multilayer interconnect implementation of the AHB protocol designed for higher performance and higher frequency systems.

Address Mapping

The following are the base addresses of memories and high-speed peripherals.

MCU AHB Secondary Address Mapping

The following are the base addresses of all low-speed MCU peripherals.

MCU APB Peripherals Address Mapping

The following are the base addresses of all low-speed ULP MCU peripherals.

ULP MCU APB Peripherals Address Mapping

Power Architecture

The Power Control Hardware implements the control sequences for transitioning between different power states (Active/Standby/Sleep/ Shutdown) and the power control for different group of peripherals. In addition, wakeup from any of the Standby/Sleep/Shutdown states based on hardware events or peripheral interrupts is supported. The Standby and Shutdown states can be reached from Active mode only through a Wait for Interrupt (WFI) instruction. Wakeup from Standby/Sleep/Shutdown states is through a hardware event or interrupt (Peripheral or External).

Highlights

• Two integrated buck switching regulators enable efficient Voltage Scaling across wide operating mode currents.
• High performance and ultra-low-power MCU peripheral subsystems and buses.
• Multiple voltage domains with independent voltage scaling of each domain.
• Fine grained power-gating including peripherals, buses and pads, thereby reducing power consumption when the peripheral/buses/ pads are inactive.
• Multiple active states using "gear-shifting" approach based on processing requirements, thereby reducing power consumption for low-power applications.
• Flexible switching between different active states with controls from software.
• Hardware based wakeup from Standby/Sleep/Shutdown states.
• All the peripherals are clock gated by default, thereby reducing the power consumption in inactive state.
• Wakeup times are configurable by software before going into sleep.

Power Domains

All the applications, high-speed interfaces, and peripherals are segregated into multiple power domains to achieve lower current consumption when they are inactive. At reset, all the domains are powered ON.

The following table describes the different group of peripherals for which power is controlled through software.

The SRAM is also segregated into multiple power domains to achieve lower current consumption per the memory requirement. The power for the SRAM domains in active states can be controlled in the following manners:

• Shut-Down Mode/Deepsleep without Retention Mode: SRAM domains as described in the following table can be powered down for unused SRAM sections. This is configurable on a bank granularity. The RAM contents of powered down sections are not retained.
• Deep-Sleep (Lower Power Consumption) Mode: No SRAM contents are retained in this mode, and the SRAM is not accessible in this state.

The following table describes the segregation of power domains for SRAM (328 KB).

Voltage Domain

All the applications, high-speed interfaces, and peripherals are segregated into multiple voltage domains to configure the operating voltages in different power states. This section describes the voltage domains and voltage source options available for each domain. These are configured based on the power state in which the device is operating. The voltage for each domain can be shut-off during sleep by configuring the source to SoC LDO (This supply is turned OFF during Sleep).

The following table lists the different voltage sources and the possible output voltages of each source at different power states.

The following table lists the different voltage domains and the possible voltage sources for each domain.

Power States

The power states available in different power modes (PS0, PS1, PS2, PS3, PS4) are listed below

• Reset State

• Active States

  • Power State1 (PS1)
  • Power State2 (PS2)
  • Power State3 (PS3)
  • Power State4 (PS4)

• Standby States

  • PS2-STANDBY
  • PS3-STANDBY
  • PS4-STANDBY

• Sleep States

  • PS2-SLEEP
  • PS3-SLEEP
  • PS4-SLEEP

• Shutdown States

  • Power State0 (PS0)

After reset, the M4 processor starts in the PS4 state which is the highest activity state where the full functionality is available. The other active states (PS2/PS3) will have limited functionality or processing power.

A transition from active states (PS2/PS3/PS4) to any other state (Sleep/Standby) can only be triggered by software.

A transition from Standby/Sleep/Shutdown states can be triggered by an enabled interrupt as configured by software before entering these states.

A transition from Standby/Sleep to active state is possible from where these states are entered. There are different wakeup sources available in each Standby/Sleep/Shutdown state.

The following shows the transitions between different power states.

PS4

This is an active state where the complete functionality is available. The CPU, peripherals, and SRAM operate on the SoC LDO supply at voltage of 1.15 V.

The functionalities available in this state are mentioned below:

• Maximum CPU operating frequency of 180 MHz. The CPU can operate on the HIGH-FREQ-PLL output clocks.
• APPLICATIONS - DEBUG, FPU, ICACHE, and ROM.
• HIGH SPEED INTERFACE - as listed in Power Domains.
• HIGH-FREQ-PLL - as listed in Power Domains.
• All the peripherals consisting of HP-PERIPHERALS, ULP-PERIPHERALS, Ultra Ultra Low Power (UULP-PERIPHERALS), and Ana- log-PERIPHERALS - as listed in the power domains section above.
• All GPIOs: 30 (GPIO) + 10 (ULP_GPIO) + 3 (UULP_VBAT_GPIO)
• Complete SRAM of up to 328 KB (320 KB Low Power (LP)-SRAM and 8 KB ULP-SRAM).
• PS4 wakeup time is around 1.2 ms

PS3

This is an active state where the complete functionality is available, similar to PS4 state, but it operates at a lower voltage, thereby reducing current consumption. The CPU, peripherals, and SRAM operate on the SoC LDO supply with output voltage of 1.05 V. The Maximum CPU frequency is limited to 90 MHz in this state.

PS2

This is an active state where a limited set of functionality is available, and the device operates at a much lower voltage compared to PS3/PS4, thereby achieving lower current consumption. The CPU, peripherals, and SRAM can operate at different voltages and are configurable by software before entering this state.

The functionalities available in this state are mentioned below:

• CPU operating frequency depends on the voltage source selected for PS2 state. The CPU operates on the ULP-Peripheral AHB Interface clock.

  • If LDO 0.75 V is used, maximum frequency is 20 MHz.
  • If SC-DC 1.05 V is used, maximum frequency is 32 MHz.
• APPLICATIONS - DEBUG, FPU, and ROM.
• Limited peripherals consisting of ULP-PERIPHERALS, UULP-PERIPHERALS and Analog-PERIPHERALS - as listed in Power Domains.
• 13 GPIOs are available - 10 (ULP_GPIO) + 3 (UULP_VBAT_GPIO)
• Total SRAM of up to 328 KB (320 KB Low Power (LP)-SRAM and 8 KB ULP-SRAM).
• PS2 wakeup time is around 200 μs

PS1

This state can be entered from PS2 only through a software instruction. The CPU is power-gated, and a limited set of peripherals are active. The peripheral interrupts are used as wakeup sources or to trigger sleep once the peripheral functionality is complete. The peripherals and SRAM operate at the same voltage as the PS2 state. The peripherals need to be configured by the software for the de- fined functionality in the PS2 state before entering this state.

The functionalities available in this state are mentioned below:

• Limited peripherals consisting of ULP-PERIPHERALS, UULP-PERIPHERALS, and Analog-PERIPHERALS - as listed in Power Domains.
• 13 GPIOs are available - 10 (ULP_GPIO) + 3 (UULP_VBAT_GPIO)
• SRAM of 320 KB (Low Power (LP)-SRAM) can be retained in this state.
• SRAM of 8 KB (ULP-SRAM) is active for peripheral functionality.

STANDBY

This includes multiple states: PS4-STANDBY, PS3-STANDBY, and PS2-STANDBY. These are standby states entered from PS4/PS3/PS2 states through a WFI instruction. CPU is clock gated in this state.

All the interrupts in the NVIC table will act as a wakeup source in the PS4-STANDBY and PS3-STANDBY states. Wakeup sources for the PS2-STANDBY state are defined in the wakeup sources section below. See Wakeup Sources for details.

SLEEP

This includes multiple states: PS4-SLEEP, PS3-SLEEP, and PS2-SLEEP. These sleep states can be entered from the PS4, PS3, and PS2 states respectively through a software instruction.

The status of resources in this state are as follows:

• UULP-PERIPHERALS and Analog-PERIPHERALS are available and are configured before entering this state.
• 3 GPIOs are available - 3 (UULP_VBAT_GPIO)
• SRAM can be retained.

Wakeup sources for these states are defined in Wakeup Sources. While transitioning from sleep to active state, all the configuration related to peripheral registers are set to default.

PS0

This is a shutdown state entered from PS2, PS3, or PS4 state through a software instruction. The CPU is power-gated, and a much smaller set of peripherals are available.

The status of resources in this state are

• UULP-PERIPHERALS and Analog-PERIPHERALS are available and are configured before entering this state.
• 3 GPIOs are available - 3 (UULP_VBAT_GPIO)
• SRAM can not be retained.

Memory Retention in Sleep / Shutdown States

The following table indicates the SRAM banks and Backup Register Array which can be retained in each Sleep/Shutdown state.

Wakeup Sources

The following table indicates the wakeup sources available in Standby/Sleep/Shutdown states.

System Power Supply Configurations

The SL917 module supports highly flexible power supply configurations for various application scenarios. Two application scenarios are listed below.

• 3.3 V single supply - A single 3.3 V supply derived from the system PMU can be input to all I/O supplies.
• 1.8 V and 3.3 V supply - A 1.8 V supply derived from the system PMU can be input to all I/O supplies except VBATT. A 3.3 V supply derived from system Power Management Unit (PMU) can be fed to the power amplifier supply pin VBATT.

Power Management

The SL917 module has an internal power management subsystem, including DC-DC converters and linear regulators. This subsystem generates all the voltages required by the module to operate from a wide variety of input sources.

• Input voltage (3.3 V) on pin VBATT
• Input voltage (1.8 V or 3.3 V) on pin IO_VDD, SDIO_IO_VDD and ULP_IO_VDD
• Input voltage (1.8 V) on pin FLASH_IO_VDD
• Nominal Output - 1.8 V and 48 mA maximum load on pin 1V8_LDO

Digital and Analog Peripherals and Interfaces

In addition to the wireless interfaces, the SL917 provides a rich set of peripherals and interfaces - both digital and analog - thus enabling varied systems and applications. The following are the categories of the peripherals and interfaces, description of each category, and list of the peripherals in that category.

Digital Peripherals and Interfaces

 I2C

• Up to three I2C primary/secondary controllers - two in MCU HP peripherals and one in the MCU ULP subsystem
• I2C standard compliant bus interface with open-drain pins
• Configurable as Primary or Secondary
• Four speed modes: Standard Mode (100 kbps), Fast Mode (400 kbps), Fast Mode Plus (1 Mbps), and High-Speed Mode (3.4 Mbps)
• 7 or 10-bit addressing
• 7 or 10-bit combined format transfers
• Support for Clock synchronization and Bus Clear
• Programmable SDA Hold time

The I2C controllers also support additional features listed below to reduce the load on the M4 processor:

• Integrated transmit and receive buffers with support for DMA
• Bulk transmit mode in I2C Secondary mode
• Interrupt based operation (polled mode also available)

UART/USART

• Up to two UART and one USART controllers
• 9-bit serial data support
• Multi-drop RS485 interface support
• 5, 6, 7, and 8-bit character encoding with even, odd, and no parity
• 1, 1.5 (only with 5 bit character encoding) and 2 stop bits
• Hardware Auto flow control (RTS/CTS)

The UART controllers also support additional features which are listed below and which help in achieving better performance and reducing the burden on the M4 processor:

• Programmable fractional baud rate support
• Programmable baud rate supporting up to 5 Mbps
• Programmable FIFO thresholds with maximum FIFO depth of 16 and support for DMA
• Prioritized interrupt identification

The following features are supported by the USART controller in the MCU HP peripherals (USART0):

• Support for both synchronous and asynchronous modes.
• Supports full duplex and half duplex (single wire) mode of communication.
• 5-8 bit wide character support.
• Supports programmable baud rates up to 20 Mbps in synchronous mode
• Programmable FIFO thresholds with maximum FIFO depth of 16 and support for DMA
• Supports generation of interrupt for different events.

The UART controller in the MCU ULP subsystem (ULP_UART) supports the following additional power-save features:

• After the DMA is programmed in PS2 state for UART transfers, the MCU can switch to PS1 state (M4 processor is turned off) while the UART controller continues with the data transfer
• In PS1 state (ULP Peripheral mode) the UART controller completes the data transfer and, triggered by the peripheral interrupt, shifts to the PS2 active state.

I2S / PCM

• Up to two I2S controllers
• Each I2S supports PCM mode of operation
• The I2S0 supports two stereo channels while the ULP_I2S and the NWP/Security subsystem I2S support one stereo channel
• Programmable audio data resolutions of 12, 16, 20, 24, and 32 bits.
• Supported audio sampling rates are 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96, and 192 kHz
• Support for primary and secondary modes
• Full duplex communication due to the independence of transmitter and receiver

The PCM mode of operation supports the following additional features:

• Mono audio data is supported
• Supports two modes for data transmission with respect to the Frame Synchronization signal – the MS bit is transmitted in the same clock cycle that the Frame Synchronization signal is asserted or one clock cycle after the Frame Synchronization signal is asserted
• Programmable FIFO thresholds with maximum FIFO depth of 8 and support for DMA
• Supports generation of interrupts for different events

The I2S in the MCU ULP subsystem supports the following additional power-save features:

• After the DMA is programmed in PS2 state for I2S transfers, the MCU can switch to PS1 state (M4 processor is turned off) while the I2S controller continues with the data transfer
• In PS1 state (ULP Peripheral mode) the I2S controller completes the data transfer and, triggered by the Peripheral Interrupt, shifts to the PS2 active state.

Quadrature Encoder Interface (QEI)

• Tracks encoder wheel position
• Programmable for 1x, 2x, or 4x position counting. Increments/decrements depending on direction.
• Index counter for revolution counting
• Velocity capture using built-in timer
• Supports position counter reset for rollover/underflow or index pulse
• Position, index, and velocity compare registers with interrupts
• Supports logically swapping the A and B inputs
• Accepts decoded signal inputs (clock and direction) in timer mode

Motor Control PWM (MCPWM)

• Part of the MCU HP peripheral subsystem
• Supports up to eight PWM outputs with four duty cycle generators
• Complementary and independent output modes are supported
• Dead time insertion in complementary mode
• Manual override option for PWM output pins. Output pin polarity is programmable.
• Supports generation of interrupt for different events
• Supports two hardware fault input pins
• Special event trigger for synchronizing analog-to-digital conversions

Synchronous Serial Interface (SSI) Primary

• Up to two Synchronous Serial Interface (SSI) primaries
• The SSI_MST provides an option to connect up to four secondaries and supports single, dual, and quad modes.
• The SSI_ULP supports single-bit mode and can be connected to only one secondary
• Programmable receive sampling delay

In addition to the above features, the SSI primaries reduce the load on the M4 processor by supporting the features below:

• Programmable FIFO thresholds with maximum FIFO depth of 16 and support for DMA
• Supports generation of interrupt for different events
• Programmable division factor for generating SSI clock out

The SSI_ULP supports the following additional power-save features:

• After the DMA is programmed in the PS2 state for SSI transfers, the MCU can switch to PS1 state (M4 processor is turned off) while the SSI primary continues with the data transfer.
• In PS1 state (ULP Peripheral mode), the SSI primary completes the data transfer and, triggered by the peripheral interrupt, shifts to the PS2 active state.

 Synchronous Serial Interface (SSI) Secondary

• Support for SSI Primaries which comply with Motorola SPI, TI SSP and National Semiconductors Microwire protocols
• Programmable FIFO thresholds with maximum FIFO depth of 16 and support for DMA
• Supports generation of interrupt for different events

Secure Digital I/O (SDIO) Secondary Interface

• Full throughput with SDIO 1.2 as well as with SDIO 2.0
• Supports up to 50 MHz
• Supports full-speed and high speed modes
• Supports SD-1 bit and SD-4 bit modes
• Supports up to five functions
• Supports interrupt for host abort, CRC Error, CMD52 and CMD53 interrupts
• Supports single as well as multiple block transfers for CMD53 access
• Supports CMD52 while CMD53 data transfer is in progress
• Supports CMD52 Abort
• Supports Read Wait
• Does not support Suspend/Resume
• Provides primary and secondary interfaces on system side AHB Bus
• Supports CIS memory configuration during boot up
• Supports system soft reset from host

There is a constraint on the minimum SoC clock relative to SDIO clock. SoC clock has to be a minimum half of SDIO clock. This constraint is due to the synchronization mechanism used between the SoC clock domain and SDIO clock domain.

HSPI Secondary

• 4-pin serial interface
• Supports 8-bit and 32-bit data
• Supports frequencies up to 100 MHz
• SPI clock can be at the max 4 times higher than AHB clock
• Support for DMA
• Supports AHB interface for accessing data from SoC
• Supports system soft reset from external host

 State Configurable Timer (SCT)

• Supports 1 configurable input and 2 output signals.
• Supports one 32-bit configuration timer
• 32-bit timer can be configured to contain one 32-bit or two 16-bit timers. The timer accepts clocks or events as input tick.
• Wide range of features like starting the counter, stopping the counter, continuing the counter from the stopped value, halt, increment the counter and capturing the events
• Support for PWM signals as output with any cycle/pulse length and superimpose a waveform on the PWM signal. It can start the ADC at any time in sync with PWM signal
• Support for DMA flow control
• Generates interrupt for different events

CRC Accelerator

• Part of MCU HP peripheral subsystem
• Support for one 32 bit polynomials
• Support for one 32 bit stream-in data widths
• Supports DMA flow control

Enhanced GPIO (EGPIO)

• Two EGPIO controllers - one in MCU HP and MCU ULP subsystem
• Supports various alternate functions like set, clear, toggle on all the pins
• Option to program Mode for each GPIO pin independently
• Supports edge and level detection based interrupt generation

Generic SPI (GSPI) Primary

• Part of MCU HP peripheral subsystem
• Supports single bit SPI primary mode.
• Support for Mode-0 and Mode-3 (Motorola)
• Supports both Full speed and High speed modes
• SPI clock out is programmable to meet required baud rates
• Support for full duplex mode
• Connect up to three SPI peripheral devices
• Support byte swapping during read and write operation
• Support up to 32 KB of read data from a SPI device in a single read operation
• Programmable FIFO thresholds with maximum FIFO depth of 16 and support for DMA
• Generates interrupt for different events

 Hardware Random Number Generator (HRNG)

• Part of MCU HP peripheral subsystem
• Supports 32-bit True Random Number Generator
• Supports 32-bit Pseudo Random Number Generator
• Option to selectively enable these random number generators

General Purpose DMA (GPDMA)

• Two primaries interface over AHB bus
• Supports 8 channels
• Linked-list based descriptors
• Has two AHB primaries for parallel data transfer. The Primary is selectable for descriptor fetch, per channel and per source and destination
• Dynamically configurable FIFO for 8 channels
• Programmable source and destination burst sizes
• Programmable beats per bursts
• Source and Destination address alignment
• Programmable Transfer Types: Memory to Memory, Memory to Peripheral and Peripheral to Memory
• Programmable priority encoded arbiter
• Supports generation of interrupt for different events
• Support for DMA squash
• Support for memory Zero Fill and One Fill

 Micro DMA (μDMA)

• Supports 32 channels
• Each DMA channel has dedicated handshake signals and programmable priority level
• Supported transfer types: memory-to-memory, memory-to-peripheral, peripheral-to-memory
• Supports multiple DMA cycle types and transfer data widths
• Programmable number of transfers in a single DMA cycle
• Average throughput is four cycles per one word reading
• Each DMA channel can access a primary, and alternate, channel control data structure
• Supports generation of interrupt for different events
• Support half-word (16 bit) and word (32 bit) size transfers

eFuse Controller

• Provides 32 bytes eFuse as one-time programmable memory locations
• Supports eFuse programming and read operations
• Supports memory mapped and FSM based read operation

SPI Flash Controllers

A serial flash device is a non-volatile memory that can be electrically erased and reprogrammed. It is used for storing executable code or data readily available for M4/NWP processor. After power-up, the executable code is read by the M4/NWP processor from the serial flash and then executed. The code in the serial flash is write-protected and cannot be altered.

Serial flash memories are controlled by many kinds of serial interface protocols (SPI, SSP, SSI, SMI, etc.). The SL917 supports SPI based flash. SPI flash memory is a secondary device.

To access it, dedicated QSPI flash controller is present which is Primary.

The SL917 has a QSPI flash controller which has 2/4/8 - wired interface for serial access of data from flash. The QSPI controller can be used in either single, dual, quad or octal modes with support for SDR to read the processor's instructions and for data transfers to/ from the flash. The controller supports inline decryption of encrypted instructions read from the flash before they are passed on to the M4/NWP processor's instruction cache. Instructions are read using the Direct Access mode while data transfers use the Indirect Access mode in case of the flash. The QSPI controllers in the MCU have been designed with programmable options for most of the single and multi-bit operations so that it can interface with flash ICs. The Direct Access mode is used to read instructions and data directly from flash. It supports inline decryption using an AES engine for the instructions or data transfer with flash. The Indirect Access mode is used to read and write data/instructions from flash. The two modes - Direct Access and Indirect Access - can be used to access the same flash or two different flashes (using CSN0 and CSN1) at a time by enabling hardware controlled mode. The QSPI controllers have independent AHB secondaries for these modes of access.

The SL917 can use a single common SPI flash for executing instructions by both NWP and M4 processors. Each processor has dedicated QSPI flash controller. Dynamic arbitration has taken place between two controllers without any processor intervention for executing instructions from common flash. Arbitration multiplexes the two SPI interfaces into a single SPI interface connected to the flash. The flash memory is partitioned into two parts dedicated to each processor respectively.

There are two flash configurations available, as shown in the figures below.

In the common flash configuration, flash is shared between both NWP and M4 processors. flash Initialization, configuration, program and erase can be done only by NWP processor. M4 processor can do only instruction fetching in direct access mode. Flash memory is divided into two regions, one each for the processor. M4 can only read M4 assigned memory region. NWP has no restriction and it can access complete flash memory.

In the dual flash configuration, each processor has its own dedicated flash memory. In this configuration, M4 can access complete flash memory. M4 can perform flash initialization, configuration, programming and erase.

The features of the SPI flash primary controller are given below.

• Supports Single/Dual/Quad/Octal (S/D/Q/O) modes for reading M4/NWP processor instructions and data transfers to/from flash.
• Support for SPI Mode-0 and Mode-3
• Support for SDR mode flash
• Supports both 8 and 16-bit flash commands.
• Support both 24 and 32-bit addressing modes
• Supports inline decryption (AES) in XTS/CTR mode with 128-bit and 256-bit key sizes while reading encrypted instructions from the flash
• Supports up to two flashes connected to CSN0 and CSN1

• Direct Access Mode:

  • Instructions are read from flash using the Direct Access mode which does not need any processor involvement after the initial configuration of the controller. The read command used for this mode is programmable depending on the flash used.
  • Direct Access mode supports Wrap / Incremental / Single read operations.
  • Supports prefetch option - enabling this option makes the SPI controller prefetch the next instruction before the request is posted on the internal AHB bus. If the address for the next instruction is different from the prefetch address, the instruction is scrapped.
  • Supports continuous fetch option to reduce instruction fetch delay from flash - this option makes the SPI controller to post the Command and Address only once on the bus to read contiguous instructions by controlling only the CSN.
  • Supports programmable CSN high time.

• Indirect Access Mode:

  • Configuration of flash and reading/writing data from/to the flash uses the Indirect Access mode which requires the M4/NWP processor to program the SPI flash controller for each access.
  • Supports reading of up to 32 KB of data from flash in a single read operation.
  • In addition to 24 and 32-bit addressing, the SPI controller supports 9, 10 and 16-bit addressing in this mode.
• Common flash mode - flash can be accessed by both MCU and NWP simultaneously

• Clock Configuration

  • Support for selection of source clock between AHB bus clock and PLL clock.
  • Support for even division factors up to 64 to generate the SPI clock from the source clock.
• Transmission of Extra-byte after the address phase is supported. The contents of this byte are programmable. There is also an option to only transmit the first nibble of the extra byte and maintain a Hi-z on the bus for the next nibble.
• Each phase of a Read operation (Command, Address, Dummy Byte, Extra Byte, Read Data) can be in any of the S/D/Q/O modes depending on the flash requirements.
• The number of dummy bytes is programmable and can be programmed as per the instruction and the mode of operation.
• Supports DMA flow control and programmable FIFO thresholds
• Supports interrupt generation based on different events
• Supports dual flash mode - reading of data from two flashes simultaneously
• Supports flash Write Protect

The SPI controller in the MCU has been designed with programmable options for most of the single and multi-bit operations so that it can interface with flash ICs from multiple vendors.

SPI PSRAM Controllers

For applications that require additional RAM, an additional external RAM can be added in the form of pseudo static RAM (PSRAM). The PSRAM is an additional RAM of size that is selected e.g. 2/4/8/16 MB.

PSRAM memory is a QSPI secondary device. M4 microcontroller communicates with the PSRAM through dedicated Quad SPI Primary controller.

The SL917 has SPI PSRAM controller which has 2/4/8 - wired interface for serial access of data from PSRAM. Dedicated SPI controllers are present for PSRAM. It can be used in either Single, Dual or Quad modes with support for SDR to read the M4 processor's instructions and for data transfers to/from the PSRAM. The controller supports inline decryption of encrypted instructions read from the PSRAM before they are passed on to the M4 processor's Instruction Cache. The SPI controllers in the MCU have been designed with programmable options for most of the single and multi-bit operations so that it can interface with PSRAM ICs. The Direct Access mode is used to read instructions and read/write data directly to/from PSRAM. It supports inline decryption using an AES engine for the instructions or data transfer with PSRAM. The Indirect Access mode is used to read and write data/instructions from PSRAM. The two modes - Direct Access and Indirect Access - can be used to access the same PSRAM or two different PSRAM (using CSN0 and CSN1) at a time by enabling hardware controlled mode. The SPI controllers have independent AHB secondaries for these modes of access.

The features of SPI PSRAM Primary controller is given below.

• Supports Single/Dual/Quad (S/D/Q/O) modes for reading M4 processor instructions and data transfers to/from PSRAM.
• Support for SPI Mode-0.
• Supports full duplex mode in single-bit SPI mode. Support for HOST SPI secondary interface.
• Support for SDR mode PSRAMs
• Supports both 8 and 16-bit PSRAM commands.
• Support both 24 and 32-bit addressing modes
• Supports only AES CTR mode encryption and decryption of PSRAM data with 128-bit and 256-bit key sizes
• Supports up to two PSRAMs connected to CSN0 and CSN1
• Supports Direct mode write
• Supports semi direct mode read operation for PSRAM

• Direct Access Mode:

  • Data transfer from/to PSRAM using the Direct Access mode which does not need any M4 processor involvement after the initial configuration of the controller. The read/write command used for this mode is programmable depending on the PSRAM used.
  • Direct Access mode supports Wrap / Incremental / Single read operations.
  • Supports prefetch option - enabling this option makes the SPI controller prefetch the next instruction before the request is posted on the internal AHB bus. If the address for the next instruction is different from the prefetch address, the instruction is scrapped.
  • Supports continuous fetch option to reduce instruction fetch delay from PSRAM - this option makes the SPI controller to post the Command and Address only once on the bus to read contiguous instructions by controlling only the CSN.
  • Supports programmable CSN high time.

• Indirect Access Mode:

  • Configuration of PSRAM and reading/writing data from/to the PSRAM uses the Indirect Access mode which requires the M4 processor to program the SPI controller for each access.
  • Supports reading of up to 32 KB bytes of data from PSRAM in a single read operation.
  • In addition to 24 and 32-bit addressing, the SPI controller supports 9, 10 and 16-bit addressing in this mode.

• Clock Configuration

  • Support for selection of source clock between AHB bus clock and PLL clock.
  • Support for even division factors up to 64 to generate the SPI clock from the source clock.
• Each phase of a Read operation (Command, Address, Dummy Byte, Extra Byte, Read Data) can be in any of the S/D/Q/O modes depending on the PSRAM requirements.
• The number of dummy bytes is programmable and can be programmed as per the instruction and the mode of operation.
• Supports DMA flow control and programmable FIFO thresholds
• Supports configurable memory ranges on which we can save code in encrypted form and the execution will happen with inline decryption.
• Supports dual PSRAM mode - reading and writing from/to two PSRAM simultaneously
• Supports interrupt generation based on different events

The SPI controllers in the MCU have been designed with programmable options for most of the single and multi-bit operations so that it can interface with PSRAM ICs from multiple vendors.

FLASH and PSRAM Supply Connections

There are four unique configuration options for flash and PSRAM connection to the SL917

1. In-package Flash/PSRAM
2. Only external Flash
3. In-package PSRAM and External Flash
4. In-package Flash and External PSRAM

For these combinations, either the in-package Flash LDO supply or an external supply can be used. The flash supply, PSRAM supply and I/O supply configurations are different for each case.

For additional modes of operation, please refer to AN1494: SiWx917 External Flash and PSRAM Application Note

Examples of supported flash and PSRAM devices are given in the following tables. For the latest up-to-date list of supported devices, consult AN1494: SiWx917 External Flash and PSRAM Application Note.

Options 1 through 4 are shown in the following diagrams. Different blocks shown in the diagrams have the following purposes:

• VBATT - 3.3 V or 1.8 V input supply connected to UULP_VBATT_1, UULP_VBATT_2, and RF_VBATT supply pins.
• SCDC - This block generates a 1.05 V voltage rail which supplies the sleep state machine, always-ON domains and other internal digital blocks.
• SoC LDO - This block generates the supply voltage for many of the digital blocks on chip. Output varies based on power state.
• Flash LDO - This block generates a 1.8 V supply for in-package and/or external flash and PSRAM.
• LC Buck - This block generates a 1.45 V supply rail for RF circuits and the SoC LDO.

Option 1: All supplies are In-package

In this configuration, the on-chip LC Buck converter powers the SoC LDO, and the on-chip Flash LDO is used as a 1.8 V supply to both flash and PSRAM.

Option 2: PSRAM supply is External and other supplies are In-package

In this configuration, the on-chip LC Buck converter powers the SoC LDO, the on-chip Flash LDO is used as a 1.8 V supply to flash, and an external 1.8 V supply is connected to the PSRAM.

Option 3: External Buck and flash / PSRAM supplies

In this configuration, an external 1.8 V supply is connected to the PSRAM.

In this configuration, an external PMIC or Buck DCDC converter powers the SoC LDO,and an external 1.8 V supply is connected to flash and PSRAM.

Option 4: PSRAM supply is External with weak pull-up on CS pin and other supplies are on-chip

In this configuration, the on-chip LC Buck converter powers the SoC LDO, the on-chip Flash LDO is used as a 1.8 V supply to flash, and an external 1.8 V supply is connected to the PSRAM. Additionally the PSRAM chip select (CSn) has an external weak pull-up resistor to the supply.

Watchdog Timer

The WatchDog Timer is used to generate an interrupt on timeout and a reset in case of system failure which can be caused by an external event like ESD pulse or due to a software failure. Also the Interrupt can be used as a Wakeup source for transitioning from SLEEP/STANDBY to ACTIVE states.

• Independent watchdog timer.
• Interrupt is generated before the system reset is applied which can be used as a wakeup source.
• Generates reset upon Lockup indication from M4 processor.
• Configurable low frequency clock (RC and Xtal).
• Configurable timeout period.
• Able to operate when CPU is in SLEEP state during power-save applications
• Individually controllable power domain for low-power applications.

Calendar

Calendar block acts a RTC with time in seconds, minutes, hours, days, months, years and centuries. The real-time can also be read through APB with accuracy less than a second by reading the millisecond count value and further less also by reading the number of counts of APB clock in 1 millisecond of RTC clock. Accuracy is high.

• Calendar block can provide a seconds trigger and also a msec trigger.
• Calendar block takes care of no. of days in each month and also leap years. It can count up to 4 centuries.
• Real time is readable through APB and also programmable through APB.

 General Purpose Timers

The MCU Timer block supports four 32 bit timers, which can be used to generate various timing events for the software. Each of the four timers can be independently programmed to work in periodic or one-shot mode and can be configured either as a microsecond timer or as a counter.

• Four independent 32 bit timers
• Supports per timer enable and disable.
• Option to configure each timer as a 32 bit counter or 32 bit microsecond timer.
• Supports 1 µs mode and 256 µs modes per timer.
• Accounts for integral and fractional value of the time units programmed.
• Microsecond timer supports two modes:
• 1 microsecond mode: The time unit is 1 µs. Number of microseconds required to be counted has to be programmed.
• 256 microsecond mode: The time unit is 256 µs. Number of 256 µs units required to be counted has to be programmed. This is useful when the timer is being used for counting large time values and microsecond based tracking not required.
• One shot and periodic modes per timer.
• Option to interrupt the M4 processor on timeout.

 Secure Storage

The Block is used for storing configuration values with data protection feature.

• MCU has 3 set's for storage block
• First chunk is 64 bits
• Second chunk is 64 bits
• Third Chunk is 128 bits
• Each chunk is a power domain.
• Secure mode is available for first and second Chunk.
• Storage space can be used for storing Configuration values

MVP

The Matrix Vector Processor (MVP) offloads floating point operations, particularly matrixed complex floating point multiplies and additions. The MVP was designed to offload the major computations of the Angle-of-Arrival (AoA) MUSIC algorithm, although the architecture can generally be used to offload other heavily floating-point computational problems such as Machine Learning (ML), Eigen, or BLAS acceleration.

• Instruction Set Architecture (ISA)

  • General purpose instruction set tailored towards algorithms built out of ALU, loop, and load/store instructions

  • Enables many high-level array functions, e.g.:

    • Matrix multiplication
    • Element-wise matrix multiplication
    • Matrix addition
    • Power series generation
    • Convolution

  • Program flexibility allows efficient iteration over N-dimensional array elements, including in-place processing of special matrix views:

    • Element-wise negate / conjugate
    • Transpose / adjoint / reverse
    • Matrix blocks (i.e., rectangular parts of matrix)
    • Matrix slices (i.e., taking rows, columns, or elements uniformly spaced within a matrix)
    • Row-major or column-major ordering

• Arithmetic Logic Unit (ALU)

  • Support for floating point real and complex numbers

    • Partial integer input support

      • Floating-point output operands, interpreted as 16-bit real or 32-bit complex number (16-bit real and 16-bit imaginary)
      • Register bank to hold all input/output operands
    • Includes 8 registers for temporary storage and/or accumulation

  • Hardware to support 1 complex floating point multiply-accumulate (MAC) per cycle

    • Four single-precision floating-point multipliers
    • Four single-precision floating-point adders
    • 6x performance of Cortex M33 FMAC operations

  • Operations supported at a rate of one operation per cycle:

    • Complex addition, multiplication, and MAC operations
    • Parallel real multiplication and MAC
    • Parallel real addition
    • Sum of 4 reals
    • Squared-magnitude of complex/real
    • Integer-to-float conversion
    • Conditional computation

  • Input transformations (per real/complex part of each input)

    • Negation (complex conjugate)
    • Zero-masking (real/imaginary part decomposition)

• Load/Store Unit (LSU)

  • Controls data streaming from memory-to-ALU and vice versa
  • Pipelined architecture to support two simultaneous 32-bit memory reads and one 32-bit memory write per cycle
  • Supports signed / unsigned 8-bit integer conversion for both load and store operations

  • First-party DMA ports

    • Used by load / store unit for handling accesses to external (system) memory addresses
    • Three independent 32-bit AHB manager ports for supporting 2 read channels and 1 write channel simultaneously

• Sequencer

  • Coordinates all MVP blocks to execute a sequence of instructions provided via the programming interface
  • Handles array iteration according to instruction sequence and static array configuration
  • Handles loop iteration according to instruction sequence and static loop configuration

• Programming interface

  • Control registers for starting / stopping engine

  • Status registers about ongoing and finished instruction sequences

    • Fault status
    • Useful information for debug
  • Breakpoint and stepping controls for debug

  • Interrupts and faults

    • Instruction sequence completion
    • Bus faults
    • Loop faults
    • Array faults
• Array configuration registers
• Loop configuration registers

• Instruction queue registers

  • Array iteration
  • ALU operations
  • Looping

SYSRTC

The SYSRTC (System Real Time Clock) is a highly configurable RTC capable of serving multiple cores. It contains up to 2 groups, where the number of capture and compare channels within each group is parametrized individually. Each group has its own interrupt and configuration registers. The main idea is to save power by letting all groups share a single counter.

• 32-bit counter
• 32 kHz / 1 kHz intended operation
• Low energy mode and wake-up
• Up to 2 groups
• 1-2 compare channels per group
• 0-1 capture channel per group
• Optional debug halting
• Optional alternate interrupt/wake-up per group
• Software Reset

Analog Peripherals and Interfaces

 Capacitive Touch

• 8 input channels - all the input channels are shared with GPIOs
• 1 shield channel - To reduce sensitivity to mesh capacitance
• Capacitive input and resistor input are connected to two GPIOs each
• Programmable input clock source from the available clocks in the chip
• Controls the rate of scanning for all sensors with configurable inter sensor scan ON time
• Supports both samples streaming and cumulative average mode
• DMA capable
• 8, 16 and 32-bit pseudo-random number for generating two non overlapping streams with configurable delay
• Programmable polynomial and seed values for pseudo-random number generator
• Provides wake up indication after capacitive touch sensing

Analog to Digital Converter (ADC)

The ADC with up to 12 bits of resolution at 2.5 Msps

• 12 bit ADC Output in 2's complement representation

• GPIOs in High Power mode for ADC Operation

  • Signal Ended Mode

    • 17 External configuration selection

    • 5 Internal configuration selection

      • Internal Temperature sensor
      • 3 Opamp Outputs

  • DAC output for internal reference

    • Differential Mode
    • 8 external differential mode configuration selection

    • 4 Internal configuration selection.

      • 3 Opamp Outputs
      • DAC output for internal reference

• GPIOs in Low Power mode for ADC Operation

  • Signal Ended Mode

    • 11 External configuration selection.

    • 5 Internal configuration selection.

      • Internal Temperature sensor.
      • 3 Opamp Outputs
      • DAC output for internal reference

  • Differential Mode

    • 5 external differential mode configuration selection.

    • 4 Internal configuration selection.

      • 3 Opamp Outputs
      • DAC output for internal reference
• 10 MHz to 32 KHz allowed ADC_CLK
• Configurable DMA to support 16 channels for storing AUXADC data in ULP SRAM.
• Measurement range 0 to AUXADC_VREF (1.8 V to 3.3 V)

The ADC has five modes of operation:

• Single ended input with noise averaging
• Single ended input without noise averaging
• Differential input with noise averaging
• Differential input without noise averaging
• Shutdown mode

Digital to Analog Converter (DAC)

DAC can take 10 bit digital inputs and convert them into analog voltage within range 5*vdd/36 to 31*vdd/36. Vdd can vary from 1.8 volts to 3.63 volts.

• 10-bit resolution
• Single ended DAC
• Monotonic by design
• Max sampling frequency is 5 MHz for DAC_CLK
• Supports Operational mode and Shutdown modes

OPAMP

• 3 general purpose Operational Amplifiers (OPAMP) offering rail-to-rail inputs and outputs.
• Each of the three opamps has 2 inputs (inp, inn) and 1 output.
• opamps can take inputs from GPIOs and their outputs can be seen on GPIOs
• configured in either low power mode or high power mode

• opamps can be configured as:

  • Unity gain amplifier
  • Trans-Impedance Amplifier(TIA)
  • Non-inverting Programmable Gain Amplifier (PGA)
  • Inverting Programmable Gain Amplifier
  • Non-inverting Programmable hysteresis comparator
  • Inverting Programmable hysteresis comparator
  • Cascaded Non-Inverting PGA
  • Cascaded Inverting PGA
  • Two opamps Differential Amplifier
  • Instrumentation Amplifier

Analog Comparators

Analog comparators peripheral consists of two analog comparators, a reference buffer, a scaler and a resistor bank. Both comparators can take inputs from GPIOs.

The comparator compares analog inputs p and n to produce a digital output, cmp_out according to:

p > n, cmp_out = 1

p < n, cmp_out = 0

The following cases of comparison are possible

• Compare external pin inputs
• Compare external pin input to internal voltages.
• Compare internal voltages.

The inputs of 2 comparators can be programmed independently. The reference buffer, scaler and resistor bank are shared between the two comparators and can be enabled only when at least one of the comparators is enabled.

Temperature Sensor

A BJT-based temperature sensor is included on the device.

The BJT based sensor works for a temperature range from -40 °C to 125 °C across the supply range 1.8 V to 3.63 V. It outputs a digital word with a resolution of nearly 1 degree C. The conversion time is 2 clock cycles of ADC after turning ON the temperature sensor.

The temperature reading of the sensor is accessed by configuring the ADC inputs to temperature sensor.

Bootloader

The Bootloader controls the initial operation of the device after any form of reset. The Bootloader supports Flash programming and initial startup of the application code. Bootloader supports following features:

• Two Bootloaders - Security Bootloader and Application Bootloader
• Support for ISP (In-System Programming) through multiple interfaces - UART, SPI and SDIO
• Auto-detection of ISP interface. The host interfaces are the external peripheral interfaces over which Bootloader can receive commands or firmware when in ISP mode. The Bootloader supports UART, SPI and SDIO interfaces. Bootloader in ISP mode waits for data on any of these interfaces and can automatically detect which interface the data is being received.
• Support for secure boot
• Support for secure firmware upgrade using PUF based Roots-of-Trust (RoT)
• Anti-rollback protection. This feature prevents the firmware version from being downgraded. A new firmware is allowed to be upgraded only if it is be equal to or greater than the current firmware.
• Secure Key Management and Protection
• Support for different flash protection levels and write-protected Flash
• Secure XIP from Flash
• Fail-proof migration of current active firmware to new (update) firmware
• Public key cryptography (digital signature) based authentication

The SL917 includes two Bootloaders - Security Bootloader and Application Bootloader. The Security Bootloader runs on the Security processor and the Application Bootloader runs on the Cortex M4 processor. On any reset, execution will always start in Security Bootloader, which is responsible for all security features, ISP and firmware upgrades. Once the Security Bootloader finishes its tasks, it enables the Application Bootloader. The Application bootloader will load and execute the application and also execute wakeup sequence on wakeup from sleep.

The following are the sources, which can trigger the Bootloader:

• Primary reset (RESET_N)
• Power on reset (POC_IN)
• Watchdog reset
• Black out monitor
• Reset request through SYSRESETREQn bit in the Cortex-M4 processor
• Wake-up from Sleep

Security

Security Features

• Secure Boot
• Secure OTA Firmware update
• TRNG: Generates high-entropy random numbers based on RF noise, increasing the effort/time needed to expose secret keys
• Secure Zone
• Secure Key storage : HW device identity and key storage with PUF
• Debug Lock
• Anti Rollback : Firmware downgrade to a lower version is prohibited through OTP to prevent the use of older, potentially vulnerable FW version
• Secure XIP from flash with XTS/CTR mode
• Secure Attestation : Allows a device to authenticate its identity using a cryptographically signed token and exchange of secret keys
• Hardware Accelerators: AES128/256/192, SHA256/384/512, HMAC, RNG, CRC, SHA3, AES-GCM/ CMAC, ChaCha-poly
• Software Implementation: RSA and ECC
• Programmable Secure Hardware Write protect for Flash sectors

Secure Bootup

Key Features

• Ensures your device runs authentic code in the boot and OTA update to eliminate malware insertion threats
• Secure Immutable Bootloader in ROM.
• Authenticates signatures of all other SW using public keys.
• Protocol and Application flash images can be encrypted with separate keys.

On reset, the Security Bootloader configures the module hardware based on the configuration present in the eFuse. It also passes the required information from the eFuse to the Application Bootloader. The Security Bootloader validates the integrity and authenticity of the firmware in the Flash and invokes the Application Bootloader. It detects and prevents execution of unauthorized software during the boot sequence. The Bootloader uses public & private key based digital signatures to recognize authentic software. The Security Boot- loader provides provision for inline execution (XIP) of encrypted firmware from Flash. The Bootloader provides 3 flash protection levels which can be used to secure different sections of the Flash for different purposes:

• Protection level 1: Stored at manufacturing, not allowed to modify by the Security Bootloader
• Protection level 2: Allowed to modify by the Bootloader only, usually used to maintain secure information used/consumed by Boot- loader
• Protection level 3: Allowed to modify by the Bootloader only, usually used to maintain protected firmware images. (Minimum 8 MB of flash is required for complete NWP image protection. For 4 MB flash OPNs, only partial protection is available for NWP image).

The protection levels are written to Flash during the manufacturing process. The write-protection feature prevents the application pro- gram from changing the Flash protection levels.

The Security configurations can be enabled or disabled during the manufacturing process.

Secure XiP

• Execute SW directly from Flash instead of copying it into RAM
• Images are saved in encrypted format and decrypted using device-specific PUF intrinsic keys while executing. In-line decryption based on-the-fly AES engine (based on PUF keys). Multiple protection levels can be set for flash, including unmodifiable. XTS/CTR modes supported.

Secure Firmware Upgrade

Secure firmware upgrade via host interface :

The secure firmware upgrade feature of the Bootloader checks the authenticity of the new firmware image along with its integrity. The Bootloader automatically detects the host interface in use and configures the host interface hardware accordingly. The Bootloader up- dates the image only after successfully validating the authenticity and integrity of the image. It prevents downgrade to a lower version of firmware using the anti-rollback feature, if it is enabled. The Bootloader also supports transparent migration to a wirelessly updated im- age and protection against failures by providing recovery mechanisms.

Secure OTA :

• Secure OTA update to eliminate malware insertion threats.
• Wireless and Application image transfer over the air.
• Wireless processor authenticates the signatures of OTA image using public keys
• Bootloader copies the OTA image to primary firmware location upon successful authentication .

Secure Zone

Key Features

• Barrier between the Security/Protocol core and Application core.
• No access to the security processor, memory, and HW registers from external peripherals, including the Cortex-M4

The Secure Zone is hardware enforced isolation between the trusted and non-trusted blocks in the system. Secure zone protects the secure assets residing in secure execution environment by restricting direct access. It also provides a secure execution environment to store confidential data. The Bootloader configures Secure Zone, secure firmware upgrade and secure bootup in "Secure Zone enabled" mode. This mode is programmed during the manufacturing process.

In-System Programming (ISP)

In System Programming (ISP) is programming or reprogramming of the flash through boot loader using UART (GPIO_8, GPIO_9), SPI (GPIO_25 to GPIO_28), and SDIO (GPIO-25 to GPIO-30) interfaces. This can be done after the part is integrated on end-user board. Boot loader can be requested to boot in ISP mode by pulling down a specific GPIO pin. This pin has to be left unconnected during reset for the boot loader to bypass ISP and execute the code that is present in flash. ISP mode can be used to reprogram the flash, if the application codes use JTAG pins for functional use. On boot up, if the application code goes into a state where JTAG interface is not functioning, ISP mode can be used to gain the control and to reprogram the flash.

Debug Lock

Key Features

• Debug ports are disabled in HW by default.
• It can be enabled in SW using cryptographically secure host interface commands validated by immutable bootloader
• It allows the device's JTAG ports to be locked and unlocked.

Debug Support

MCU implements complete hardware debug solution. This provides high system visibility of the M4 processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.

In Serial Wire Viewer (SWV) mode, a one-bit serial protocol is used and this reduces the number of output signal to one. When combining SWV with Serial-Wire debug protocol, the Text Data Output (TDO) pin normally used for Joint Test Action Group (JTAG) protocol can be shared with SWV.

The Embedded Trace Macrocell (ETM) provides high bandwidth instruction trace via four dedicated trace. The MCU_CLK_OUT frequency must be in the range of 40 MHz to 90 MHz to Instruction trace using ETM component.

WLAN

• Compliant to single-spatial stream IEEE 802.11 b/g/n/ax with single band (2.4 GHz) support
• Support for 20 MHz channel bandwidth for 802.11n and 802.11ax.
• Operating Modes: Wi-Fi 4 STA, Wi-Fi 6 (802.11ax) STA, Wi-Fi 4 AP, Enterprise STA, Wi-Fi 6 STA + Wi-Fi 4 AP, Wi-Fi STA + BLE
• Wi-Fi 6 Features: Individual Target wake-up time (iTWT), Broadcast TWT (bTWT),SU extended range (ER), DCM (Dual Carrier Modulation), DL MU-MIMO, DL/UL OFDMA, MBSSID, BFRP, Spatial Re-use, BSS Coloring, and NDP feedback up to 4 antennas
• Integrated PA
• Data Rates—802.11b: up to 11 Mbps; 802.11g: up to 54 Mbps; 802.11n: MCS0 to MCS7; 802.11ax: MCS0 to MCS7
• Operating Frequency Range [MHz]: 2412-2462 (North America, default), 2412-2472 (Europe, and other countries where applicable), 2412-2484 (Japan)

MAC

• Conforms to IEEE 802.11b/g/n/j/ax standards for MAC
• Hardware accelerators for AES
• WPA, WPA2, WPA3 and WMM support
• AMPDU aggregation for high performance
• Firmware downloaded from host based on application
• Hardware accelerators for DH (for WPS) and ECDH

Baseband Processing

• Supports 11b: DSSS for 1, 2 Mbps and CCK for 5.5, 11 Mbps

• Supports all OFDM data rates

  • 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
  • 802.11ax, 802.11n: MCS 0 to MCS 7
• High-performance multipath handling in OFDM, DSSS, and CCK modes

Bluetooth

Key Features

• Transmit power up to +17 dBm with integrated PA
• Receive sensitivity — LE: -93 dBm, LR 125 Kbps: -104.5 dBm
• Operating Frequency Range — 2.402 GHz - 2.480 GHz
• Supports Bluetooth® Low Energy (LE): High Speed (1Mbps and 2Mbps) and Long Range (LE Coded PHYs, 125Kbps and 500Kbps; these are referred to as "LR" throughout this data sheet)
• Advertising extensions
• Data length extensions
• LL privacy
• LE dual role
• BLE acceptlist
• Two simultaneous BLE connections (2 peripheral or 2 central, or 1 central and 1 peripheral)
• BLE Mesh (4 nodes) for limited switch use case.

 MAC

Link Manager

• Creation, modification & release of physical links
• Connection establishment between Link managers of two Bluetooth devices
• Link supervision is implemented in Link Manager
• Link power control is done depending on the inputs from Link Controller
• Enabling & disabling of encryption & decryption on logical links
• AES hardware acceleration

Link Controller

• Encodes and decodes header of BLE packets
• Manages flow control, acknowledgment, re-transmission requests, etc.
• Stores the last packet status for all physical transports
• Indicates the success status of packet transmission to upper layers
• Indicates the link quality to the LMP layer

Device Manager

• Executes HCI Commands
• Controls Scan & Connection processes
• Controls all BLE Device operations except data transport operations
• BLE Controller state transition management
• Anchor point synchronization & management
• Scheduler

Baseband Processing

Supports BLE 1 Mbps, 2 Mbps and long range 125 kbps, 500 kbps

RF Transceiver

• The SL917 features two highly configurable RF transceivers supporting WLAN 11b/g/n/ax and Bluetooth LE wireless protocols. Both RF transceivers together operating in multiple modes covering High Performance (HP) and Low Power (LP) operations. List of operating modes are given in next section.
• It contains two fully integrated fractional-N frequency synthesizers having reference from internal oscillator with 40 MHz crystal. One of the synthesizer is a low power architecture which also caters single-bit data modulation feature for Bluetooth LE protocols.

Receiver and Transmitter Operating Modes

The available radio operating modes are

• WLAN HP TX - WLAN High-Performance Transmitter
• WLAN HP RX - WLAN High-Performance Receiver
• WLAN LP RX - WLAN Low-Power Receiver
• BLE HP TX - Bluetooth LE High-Performance Transmitter
• BLE HP RX - Bluetooth LE High-Performance Receiver
• BLE LP TX - Bluetooth LE Low-Power Transmitter
• BLE LP RX - Bluetooth LE Low-Power Receiver

Embedded Wi-Fi Software

• The wireless software package supports Embedded Wi-Fi (802.11 b/g/n/ax) Client mode, Wi-Fi Access point mode (up to 4 clients), and Enterprise Security in client mode.
• The software package includes complete firmware and application profiles.
• It has a wireless coexistence manager to arbitrate between protocols.

Security

Wireless software supports multiple levels of security capabilities available for the development of IoT devices.

• Accelerators: AES128/256
• WPA/WPA2/WPA3-Personal, WPA/WPA2 Enterprise for Client

Low Power Modes

It supports Ultra-low power consumption with multiple power modes to reduce system energy consumption.

• Voltage and Frequency Scaling
• Deep sleep (ULP) mode with only the sleep timer active – with and without RAM retention
• Wi-Fi standby associated mode with automatic periodic wake-up
• Automatic clock gating of the unused blocks or transit the system from Normal to ULP mode.

ULP Mode

In Ultra Low Power mode, the deep sleep manager has control over the other subsystems and M4 processors and controls their active and sleep states. During deep sleep, the always-on logic domain operates on a lowered supply and a low-frequency clock to reduce power consumption. The ULP mode supports the following wake-up options:

• Timeout wakeup - Exit sleep state after programmed timeout value.
• GPIO Based Wakeup: Exit sleep state when GPIO goes High/Low based on programmed polarity.
• Analog Comparator Based wakeup - Exit sleep state on an event at the analog comparator.
• RTC Timer wakeup - Exit Sleep state on timeout of RTC timer
• WatchDog Interrupt based wakeup - Exit Sleep state upon watchdog interrupt timeout.

Wireless Subsystem Memory

On-Chip Memory

The Network Wireless Processor has the following memory:

• On-chip SRAM of 672/480/416/352 KB based on chip configuration
• 448 KB of ROM which holds the Secure primary bootloader, Network Stack, Wireless stacks and security functions
• 16 KB of Instruction cache enabling eXecute In Place (XIP) with quad SPI flash memory.
• eFuse of 1024 bytes (used to store primary boot configuration, security and calibration parameters) The Following memory configuration between MCU and Wireless Sub-system are possible:

Pad Configuration

There are multiple processor sub-systems containing SZP (Secure Zone Processor), MCU HP (High Performance) and MCU ULP (Ultra Low Power) which share these common set of GPIO pads. These GPIO pads are controllable by either SZP, MCU HP or MCU ULP. PAD selection register has to be programmed to control the PAD behavior for each GPIO. The SZP and MCU HPGPIOs are available only in PS4/PS3 power states whereas MCU ULP GPIOs are available in all the power states except sleep modes. The UULP Vbat GPIOs are available in all power states.

The SZP, MCU HP and MCU ULP GPIOs PAD are programmable, multi-voltage (1.8 V, 3.3 V) general purpose, bi-directional I/O buffer with a selectable LVCMOS (Low Voltage CMOS) input or LVCMOS Schmitt trigger input and programmable pull-up/pull-down. In the full-drive mode, this buffer can operate in excess of 100 MHz frequency with 15 pF external load and 125 MHz with 10pF load, but actual frequency is load and system dependent. A maximum of 200 MHz can be achieved under small capacitive loads.

The following PAD configurations can be controlled by software for SZP, MCU HP and MCU ULP GPIOs.

• Bi-directional IO capability
• Multi-voltage DVDD capability (1.8 V, 3.3 V)
• Power-on-Start (POS) capable
• Optimized for EMC (low di/dt switching supply noise) with SSO (Simultaneous Switching Output) factor of 8
• Four (4) Programmable output drive strengths (rated 2 mA, 4 mA, 8mA, and 12 mA)
• Selectable output slew-rate (slow / fast)
• Open drain output mode (Logic low or high on input and use OEN as data input)
• LVCMOS/LVTTL compatible input with selectable hysteresis
• Programmable input options (pull-up, pull-down, repeater, or plain input)
• No power sequence requirements, I/Os are tri-stated when core power is not valid (POC control). These are tri-stated even if the system is under reset or in the deep sleep power state.

The following PAD configurations can be controlled by software for UULP Vbat GPIOs.

• Bi-directional IO capability
• Multi-voltage DVDD capability (1.8 V, 3.3 V)

Interrupts

• Nested vectored interrupt controller (NVIC) for interrupts handling
• Supports 99 interrupts
• Flexible exception and interrupt management
• Nested exception/interrupt support
• Vectored exception/interrupt entry
• Interrupt configurations, prioritization, and interrupt masking

Hardware Architecture

Block Diagrams

Pin-Out

List of IC Pins Not Available in the Modules

Chip Packages - RF and Control Interfaces

Chip Packages - Power and Ground Pins

Chip Packages - Peripheral Interfaces

GPIO Pin Multiplexing

SoC GPIO Pin Multiplexing

The SoC GPIOs shown below (GPIO_6 to GPIO_57) are available in the normal mode of operation (Power-states 4 and 3). Default mode is mode0 (Mode = 0) if not explicitly mentioned. For a description of power-states, refer to the Power States section of the Reference Manual. Each of these GPIOs Pin function is controlled by the GPIO Mode register mentioned in SoC GPIOs section of the Reference Manual.

ULP GPIO Pin Multiplexing

The ULP GPIOs shown below (ULP_GPIO_0 to ULP_GPIO_11) are available in the normal mode of operation (Power-states 4 and 3) and also in Ultra-low power mode of operation of the Microcontroller (Power-states 2 and 1). For a description of power-states, refer to the Power States section of the Reference Manual. Each of these GPIO's Pin function is controlled by the GPIO Mode register mentioned in ULP GPIO's section of the Reference Manual.

UULP VBAT GPIO Pin Multiplexing

The UULP VBAT GPIOs shown below (UULP_VBAT_GPIO_0 to UULP_VBAT_GPIO_3) are available in the normal mode of operation (Power-states 4 and 3), in Ultra-low power mode of operation (Power-states 2 and 1) and also in the retention and deep sleep mode of operation (Retention and Power-state 0). For a description of power-states, refer to the Power States section of the Reference Manual. Each of this UULP VBAT GPIO's Pin function is controlled by the GPIO Mode register mentioned in UULP VBAT GPIO's section of the Reference Manual.

Analog Functions

Analog functions are available on several of the SoC GPIO and ULP_GPIO pins. The analog functions are mapped to ULP_GPIO pins on the AGPIO_x selections, and to SoC GPIO pins on the TopGPIO_x selections shown in the multiplexing tables. A summary of signals and potential GPIO mapping are shown below.

Digital Functions

The ULP GPIOs shown below are configured for SoC peripheral functionality (SOCPERH_ON_ULP_GPIO_0 to SOCPERH_ON_ULP_GPIO_11) and are available only in the normal mode of operation (Power- states 4 and 3). For a description of power-states, refer to the Power States section of the Reference Manual. Each of these GPIO's Pin function is controlled by the GPIO Mode register mentioned in SoC GPIO's section of the Reference Manual.

The SoC GPIOs shown below are configured for ULP peripheral functionality (ULPPERH_ON_SOC_GPIO_0 to ULPPERH_ON_SOC_GPIO_11) and are available only in the normal mode of operation (Power- states 4 and 3). For a description of power-states, refer to the Power States section of the Reference Manual. Each of these GPIO's Pin function is controlled by the GPIO Mode register mentioned in ULP GPIO's section of the Reference Manual.

Valid GPIO Sets for Peripherals

Functions can be split pin wise across all GPIOs except for below restrictions. For synchronous interfaces there are some restrictions on clubbing of GPIOs into synchronous buses to ensure the timings mentioned in section SL917 module specifications. For example a single synchronous interface should not be split across ULP & SoC GPIO's. The following table shows recommended locations for each function. For GPIO mode related information refer to GPIO Pin Multiplexing.

Functional Description

Digital Functions

Analog Functions

Package Layout

Package Outline

Module Dimensions

Pin Locations

PCB Landing Pattern

PCB Landing Pattern Pin Locations

Mechanical Drawings

Heatsink (SOM Only?)

Schematics

453-00220 Schematics for Parts with RF Pin

System Supplies 

RF, JTAG, and Reset Connection

GPIO Connection

Reset

LF Clock Option

Flash Memory Configurations

PSRAM Memory Configurations

Debug and In-System Programming

Bill of Materials

Bill of Materials

SL917: External Flash & PSRAM BOM Options (these are optional and need not be used for every use-case)

453-00222 Schematics for parts with Integral Antenna

System Supplies

RF, JTAG, and Reset Connection

GPIO Connection

Reset

LF Clock Option

Flash Memory Configurations

PSRAM Memory Configurations

Debug and In-System Programming

Bill of Materials

Bill of Materials

External Flash & PSRAM BOM Options (these are optional and need not be used for every use-case)

Layout Guidelines

Electrical Characteristics

Absolute Maximum Ratings

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at https://www.silabs.com/about-us/quality .

Recommended Operating Conditions

DC Electrical Characteristics

RESET_N Pin

Power On Control (POC) and Reset

There are three signals involved in power-on control and reset of the device:

• POC_IN: When pulled low, POC_IN will reset all of the internal blocks in the device. The POC_IN signal can be controlled either by external circuitry, by POC_OUT, or both.
• RESET_N: RESET_N is an open-drain signal which will be pulled low during a chip reset. It is released after POC_IN is high. RE- SET_N should be connected to an RC circuit to fulfill the timing requirements shown below.
• POC_OUT: The POC_OUT signal is the output of the internal blackout supply monitor. POC_OUT is distributed to all I/O cells to prevent the I/O cells from powering up in an undesired configuration and is also used inside the IC to place the IC in a safe state until a valid supply is available for proper operation. During power up, POC_OUT stays low until the VBATT reaches 1.6 V. After the VBATT supply exceeds 1.6 V, POC_OUT becomes high and normal operation begins. If VBATT becomes lower than the blackout threshold voltage, POC_OUT will return low. POC_OUT can be used to provide chip reset by connecting to POC_IN in a loopback configuration.

The recommended schematic for the reset signals is shown in Figure 8.4 Reset Configuration on page 142.

Below shows the signal timing when POC_OUT, POC_IN, and RESET_N are connected per the recommended schematic. The POC_IN-to-RESET_N delay will occur when POC_IN transitions low to high.

In this configuration the system only has to control the supply (VBATT) during power-up and power down and need not control POC_IN externally. On power-up the chip will be reset internally. The power-down sequence will follow VBATT and external control of POC_IN is not required.

If the chip is to be reset from an external host device while powered up, the POC_IN signal should be pulled low for at least 10 ms as shown below. Upon release of POC_IN, the POC_IN-to-RESET_N delay will occur.

In the above timing diagrams, it is assumed that all supplies including VBATT are connected together. If they are not connected together and independently controlled, then the guidance below must be followed.

• Case1: POC is looped back and there is no external control for POC_IN

  • All supplies can be enabled at the same time, if possible
  • If supplies cannot be enabled at the same time, the VBATT supplies should be powered up first and all other supplies should be powered on at least 1 ms before RESET_N is high. The RC circuit controlling RESET_N must be adjusted to provide the appropriate delay.
  • While powering down, supplies can be powered off simultaneously, or with VBATT the last to be disabled.

• Case2: POC is looped back and there is external control for POC_IN during power-up / power-down.

  • All supplies can be enabled at the same time, or VBATT may be enabled before other supplies.
  • POC_IN should be kept low for at least 600 us after all the supplies have settled.
  • On power-down, POC_IN can be driven low before disabling the supplies. Supplies can be powered off simultaneously, or with VBATT the last to be disabled.

Blackout Monitor

The blackout comparator is enabled by default upon power up. Blackout is typically asserted when the UULP_VBATT_1 or UULP_VBATT2 (VBATT) supply goes lower than 1.6 V (see Table 7.4 Blackout Monitor Electrical Specifications on page 95), and it is de-asserted when VBATT supply goes higher than 1.625 V. The blackout monitor circuit will reset the device when POC_OUT is connected to POC_IN as recommended.

The blackout monitor will be disabled after power up. The functionality should be enabled by the SoC firmware if required in the system. The blackout monitor block should be enabled to monitor the VBATT voltage only in high power modes. In low power modes battery level detection can be implemented using the Nano-Power Brownout detection comparator.

When the system is in low power mode, the blackout comparator is automatically enabled upon a brownout event.

Blackout Monitor Electrical Specifications