BL654

Introduction

Overview

This document describes key hardware aspects of the BL654 Series modules. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the BL654 series, visit the BL654 product page.

General Description

Every BL654 Series module is designed to simplify OEMs enablement of Bluetooth Low Energy (BLE) v5.1 and Thread (802.15.4) to small, portable, power-conscious devices. The BL654 provides engineers with considerable design flexibility in both hardware and software programming capabilities. Based on the world-leading Nordic Semiconductor nRF52840 chipset, the BL654 modules provide ultra-low power consumption with outstanding wireless range via +8 dBm of transmit power and the Long Range (CODED PHY) Bluetooth 5 feature. The BL654 is programmable via Ezurio’s smartBASIC language or Nordic’s software development kit (SDK).  

smartBASIC is an event-driven programming language that is highly optimized for memory-constrained systems such as embedded modules. It was designed to make BLE development quicker and simpler, vastly cutting down time to market.

The Nordic SDK, on the other hand, offers developers source code (in C) and precompiled libraries containing BLE and ANT+ device profiles, wireless communication, as well as application examples.

Application Areas

• Medical devices
• IoT Sensors
• Appcessories
• Fitness sensors
• Location awareness
• Home automation

Features & Benefits

The BL654 device features and benefits are described below.

• Bluetooth v5.1 – Single mode
• NFC
• 802.15.4 (Thread) radio support
• External or internal antennas

• Multiple programming options

  • smartBASIC AT command set shim or
  • Nordic SDK in C
• Compact footprint
• Programmable Tx power +8 dBm to -20 dBm, -40 dBm
• Rx sensitivity – -95 dBm (1 Mbps), - 103 dBm (125 kbps)
• Ultra-low power consumption
• Tx – 4.8 mA peak (at 0 dBm, DCDC on)
  (See Note 1 in the Power Consumption section)
• Rx: 4.6 mA peak (DCDC on)
  (See Note 1 in the Power Consumption section)
• Standby Doze – 3.1 uA typical
• Deep Sleep – 0.4 uA – (See Note 4 in the Power Consumption section)
• UART, GPIO, ADC, PWM, FREQ output, timers, I2C, SPI, I2S, PDM, and USB interfaces
• Fast time-to-market
• FCC, EU, ISED, RCM and Japan certified
• Full Bluetooth Declaration ID
• Other regulatory certifications on request
• No external components required
• Industrial temperature range (-40° C to +85° C)

Specification Summary

Processor / SoC

Bluetooth

NFC

Radio Performance

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Module Specification Notes:

Functional Descriptions

WLAN Functional Description

Bluetooth Functional Description

Programming & Firmware

BL654 Default Firmware

The BL654 module comes loaded with smartBASIC firmware but does not come loaded with any smartBASIC application script (as that is dependent on customer-end application or use). Ezurio provides many sample smartBASIC application scripts via a sample application folder on GitHub –  https://github.com/EzurioCP/BL654-Applications

Therefore, it boots into AT command mode by default.

BL654 Special Function Pins in smartBASIC

Refer to the smartBASIC extension manual for details of functionality connected to this:

• nAutoRUN pin (SIO_35), see Table 6 for default
• VSP pin (SIO_02), see Table 7 for default
• SIO_38 – Reserved for future use. Do not connect. See Table 8

nAutoRUN pin

In the development board nAutoRUN pin is connected so that the state is driven by the host’s DTR output line.

VSP mode

SIO_38

Interfaces

UART

The Universal Asynchronous Receiver/Transmitter (UART) offers fast, full-duplex, asynchronous serial communication with built-in flow control support (UART_CTS, UART_RTS) in HW up to one Mbps baud. Parity checking and generation for the ninth data bit are supported.

UART_TX, UART_RX, UART_RTS, and UART_CTS form a conventional asynchronous serial data port with handshaking. The interface is designed to operate correctly when connected to other UART devices such as the 16550A. The signaling levels are nominal 0 V and 3.3 V (tracks VDD) and are inverted with respect to the signaling on an RS232 cable.

Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and UART_CTS is an input. Both are active low.

These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS are all 3.3 V level logic (tracks VDD). For example, when RX and TX are idle they sit at 3.3 V. Conversely for handshaking pins CTS, RTS at 0 V is treated as an assertion.

The module communicates with the customer application using the following signals:

• Port/TxD of the application sends data to the module’s UART_RX signal line
• Port/RxD of the application receives data from the module’s UART_TX signal line

Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend linking CTS and RTS other than for testing and prototyping. If these pins are linked and the host sends data at the point that the BL654 deasserts its RTS signal, there is significant risk that internal receive buffers will overflow, which could lead to an internal processor crash. This will drop the connection and may require a power cycle to reset the module. We recommend that the correct CTS/RTS handshaking protocol be adhered to for proper operation.

UART interface

The UART interface is also used to load customer developed smartBASIC application script.

USB

BL654 has USB2.0 FS (Full Speed, 12Mbps) hardware capability. There is a CDC driver/Virtual UART as well as other USB drivers available via Nordic SDK – such as: usb_audio, usb_hid, usb_generic, usb_msc (mass storage device).

USB interface

SPI Bus

The SPI interface is an alternate function on SIO pins.

The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CS is implemented using any spare SIO digital output pins to allow for multi-dropping.

The SPI interface enables full duplex synchronous communication between devices. It supports a 3-wire (SPI_MOSI, SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves. Individual chip select signals are necessary for each of the slave devices attached to a bus, but control of these is left to the application through use of SIO signals. I/O data is double buffered.

The SPI peripheral supports SPI mode 0, 1, 2, and 3.

SPI interfaces

I2C

The I2C interface is an alternate function on SIO pins.

The two-wire interface can interface a bi-directional wired-OR bus with two lines (SCL, SDA) and has master /slave topology. The interface is capable of clock stretching. Data rates of 100 kbps and 400 kbps are supported.

An I2C interface allows multiple masters and slaves to communicate over a shared wired-OR type bus consisting of two lines which normally sit at VDD. The SCL is the clock line which is always sourced by the master and SDA is a bi-directional data line which can be driven by any device on the bus.     

I2C interface

NFC

NFC support:

• Based on the NFC forum specification

  • 13.56 MHz
  • Date rate 106 kbps
  • NFC Type2 and Type4 tag emulation

• Modes of operation:

  • Disable
  • Sense
  • Activated

Use Cases

• Touch-to Pair with NFC
• Launch a smartphone app (on Android)
• NFC enabled Out-of-Band Pairing

• System Wake-On-Field function

  • Proximity Detection

NFC interface

NFC Antenna Coil Tuning Capacitors

From Nordic’s nRF52840 Objective Product Specification v1.0: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf

The NFC antenna coil must be the connected differential between the NFC1 and NFC2 pins of the BL654. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz. 

The required external tuning capacitor value is given by the following equations:

An antenna inductance of Lant = 0.72 uH provides tuning capacitors in the range of 300 pF on each pin. The total capacitance on NFC1 and NFC2 must be matched.  Cint and Cp are small usually (Cint is 4pF), so can omit from calculation.

Battery Protection Note: If the NFC coil antenna is exposed to a strong NFC field, the supply current may flow in the opposite direction due to parasitic diodes and ESD structures.
If the used battery does not tolerate a return current, a series diode must be placed between the battery and the BL654 to protect the battery.

GPIO

The 19 SIO pins are configurable by smartBASIC application script or Nordic SDK. They can be accessed individually. Each has the following user configured features:

• Input/output direction
• Output drive strength (standard drive 0.5 mA or high drive 5mA)
• Internal pull-up and pull-down resistors (13 K typical) or no pull-up/down or input buffer disconnect
• Wake-up from high or low-level triggers on all pins including NFC pins

ADC

The ADC is an alternate function on SIO pins, configurable by smart BASIC or Nordic SDK.

The BL654 provides access to 8-channel 8/10/12-bit successive approximation ADC in one-shot mode. This enables sampling up to 8 external signals through a front-end MUX. The ADC has configurable input and reference pre-scaling and sample resolution (8, 10, and 12 bit). 

Analog Interface (ADC)

PWM

PWM Signal Output on up to 16 SIO Pins

The PWM output is an alternate function on ALL (GPIO) SIO pins, configurable by smartBASIC or the Nordic SDK.

The PWM output signal has a frequency and duty cycle property. Frequency is adjustable (up to 1 MHz) and the duty cycle can be set over a range from 0% to 100%.

PWM output signal has a frequency and duty cycle property. PWM output is generated using dedicated hardware in the chipset. There is a trade-off between PWM output frequency and resolution.

For example:

• PWM output frequency of 500 kHz (2 uS) results in resolution of 1:2.
• PWM output frequency of 100 kHz (10 uS) results in resolution of 1:10.
• PWM output frequency of 10 kHz (100 uS) results in resolution of 1:100.
• PWM output frequency of 1 kHz (1000 uS) results in resolution of 1:1000.

FREQ

FREQ Signal Output on up to 16 SIO Pins

The FREQ output is an alternate function on 16 (GPIO) SIO pins, configurable by smartBASIC or Nordic SDK.

FREQ output signal frequency can be set over a range of 0Hz to 4 MHz (with 50% mark-space ratio).

nReset Pin

nRESET pin

Two-Wire Interface JTAG

The BL654 Firmware hex file consists of four elements:

• smartBASIC runtime engine
• Nordic Softdevice
• Master Bootloader

Ezurio BL654 smartBASIC firmware (FW) image part numbers are referenced as w.x.y.z (ex. v29.x.y.z). The BL654 smartBASIC runtime engine and Softdevice combined image can be upgraded by the customer over the UART interface.

You also have the option to use the two-wire (JTAG) interface, during production, to clone the file system of a Golden preconfigured BL654 to others using the Flash Cloning process. This is described in the following application note Flash Cloning for the BL654. In this case the file system is also part of the .hex file.

Two-wire interface JTAG

The Ezurio development board incorporates an on-board JTAG J-link programmer for this purpose. There is also the following JTAG connector which allows on-board JTAG J-link programmer signals to be routed off the development board. The only requirement is that you should use the following JTAG connector on the host PCB. 

The JTAG connector MPN is as follows:

JTAG connector MPN

JTAG is require because Nordic SDK applications can only be loaded using the JTAG (smartBASIC firmware can be loaded using JTAG as well as over the UART). We recommend that you use JTAG (2-wire SWD interface) to handle future BL654 module firmware upgrades. You must wire out the JTAG (2-wire SWD interface) on your host design (see Figure 7, where the following four lines should be wired out – SWDIO, SWDCLK, GND and VCC). smartBASIC firmware upgrades can still be performed over the BL654 UART interface, but this is slower than using the BL654 JTAG (2-wire SWD interface) – (60 seconds using UART vs. 10 seconds when using JTAG).

SWO (SIO_32) is a Trace output (called SWO, Serial Wire Output) and is not necessary for programming BL654 over the SWD interface.

nRESET_BLE is not necessary for programming BL654 over the SWD interface.

BL654 Wakeup

Waking Up BL654 from Host

Wake the BL654 from the host using wake-up pins (any SIO pin). You may configure the BL654’s wakeup pins via smartBASIC to do any of the following:

• Wake up when signal is low
• Wake up when signal is high
• Wake up when signal changes

Refer to the smartBASIC user guide for details. You can access this guide from the Ezurio BL654 product page.

For BL654 wake-up using the Nordic SDK, refer to Nordic infocenter.nordicsemi.com.

Temperature Sensor

The on-silicon temperature sensor has a temperature range greater than or equal to the operating temperature of the device. Resolution is 0.25°C degrees. The on-silicon temperature sensor accuracy is ±5°C.

To read temperature from on-silicon temperature sensor (in tenth of centigrade, so 23.4°C is output as 234) using smartBASIC:

In command mode, use ATI2024
or

From running a smartBASIC application script, use SYSINFO(2024)

Optional External 32.768 kHz crystal

This is not required for normal BL654 module operation.

The BL654 uses the on-chip 32.76 kHz RC oscillator (LFCLK) by default (which has an accuracy of ±500 ppm) which requires regulator calibration (every eight seconds) to within ±500 ppm.

You can connect an optional external high accuracy (±20 ppm) 32.768 kHz crystal (and associated load capacitors) to the BL654SIO_01/XL2 (pin 41) and SIO_00/XL1 (pin 42) to provide improved protocol timing and to help with radio power consumption in the system standby doze/deep sleep modes by reducing the time that the RX window needs to be open. Table 25 compares the current consumption difference between RC and crystal oscillator.

Comparing current consumption difference between BL654 on-chip RC 32.76 kHz oscillator and optional external crystal (32.768kHz) based oscillator

Optional external 32.768 kHz crystal specification

Be sure to tune the load capacitors on the board design to optimize frequency accuracy (at room temperature) so it matches that of the same crystal standalone, Drive Level (so crystal operated within safe limits) and oscillation margin (R_neg is at least 3 to 5 times ESR) over the operating temperature range.

Security and Privacy

Random Number Generator

Exposed via an API in smartBASIC (see smartBASIC documentation available from the BL654 product page). The rand() function from a running smartBASIC application returns a value.

For Nordic related functionality, visit Nordic infocenter.nordicsemi.com

AES Encryption/Decryption

Exposed via an API in smartBASIC (see smartBASIC documentation available from the BL654 product page).  Function called aesencrypt and aesdecrypt.

For Nordic related functionality, visit Nordic infocenter.nordicsemi.com

ARM Cryptocell

ARM Cryptocell incorporates a true random generator (TRNG) and support for a wide range of asymmetric, symmetric and hashing cryptographic services for secure applications. For more information, please check the Nordic SDK.

Readback Protection

The BL654 supports readback protection capability that disallows the reading of the memory on the nrf52840 using a JTAG interface. Available via smartBASIC or the Nordic SDK.

Eliptic Curve Cryptography

The BL654 offers a range of functions for generating public/private keypair, calculating a shared secret, as well as generating an authenticated hash. Available via smartBASIC or the Nordic SDK.

RF

• 2402–2480 MHz Bluetooth Low Energy radio BT 5.1 – 1 Mbps, 2 Mbps, and Long-range (125 kbps and 500 kbps) over-the-air data rate.
• Tx output power of +8 dBm programmable down to 7 dBm, 6 dBm, 5 dBm, 4 dBm, 2 dBm, 0 dBm and further down to -20 dBm in steps of 4 dB and final TX power level of -40 dBm.
• Receiver (with integrated channel filters) to achieve maximum sensitivity -95 dBm @ 1 Mbps BLE, -92 dBm @2 Mbps, -103 dBm @ 125 kbps long-range and -99 dBm @500kbps long-range).

• RF conducted interface available in the following two ways:

  • 451-00001: RF connected to on-board PCB trace antenna
  • 451-00002: RF connected to on-board IPEX MH4 RF connector

• Antenna options:

  • Integrated PCB trace antenna on the 451-00001
  • External dipole antenna connected with to IPEX MH4 RF connector on the 451-00002
• Received Signal Strength Indicator (RSSI)
• RSSI accuracy (valid range -90 to -20dBm) is ±2dB typical
• RSSI resolution 1dB typical

Power

Power Management

Power management features:

• System Standby Doze and Deep Sleep modes
• Open/Close peripherals (UART, SPI, QSPI, I2C, SIO’s, ADC, NFC). Peripherals consume current when open; each peripheral can be individually closed to save power consumption
• Use of the internal DCDC convertor or LDO is decided by the underlying BLE stack
• smartBASIC command allows the supply voltage to be read (through the internal ADC)
• Pin wake-up system from deep sleep (including from NFC pins)

Power supply features:

Supervisor hardware to manage power during reset, brownout, or power fail.

• 1.7V to 3.6V supply range for normal power supply (VDD pin) using internal DCDC convertor or LDO decided by the underlying BLE stack.
• 2.5V to 5.5 supply range for High voltage power supply (VDD_HV pin) using internal DCDC convertor or LDO decided by the underlying BLE stack.
• 4.35V to 5.5V supply range for powering USB (VBUS pin) portion of BL654 only.   The remainder of the BL654 module circuitry must still be powered through the VDD (or VDD_HV) pin.    

Power Supply Options

The BL654 module power supply internally contains the following two main supply regulator stages (Figure 4):

REG0 – Connected to the VDD_HV pin

REG1 – Connected to the VDD pin

The USB power supply is separate (connected to the VBUS pin).

The BL654 power supply system enters one of two supply voltage modes, normal or high voltage mode, depending on how the external supply voltage is connected to these pins.

BL654 power supply options:

• Option 1 – Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDD_HV pins (so that VDD equals VDD_HV).  Connect external supply within range 1.7V to 3.6V range to BL654 VDD and VDD_HV pins. 
  OR
• Option 2 – High voltage mode power supply mode (using BL654 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDD_HV pin and the VDD pin is not connected to any external voltage supply.  Connect external supply within range 2.5V to 5.5V range to BL654 VDD_HV pin. BL654 VDD pin left unconnected.

Nordic Errata 197 and 202 related to the use of VDD_HV DCDC convertor, for details refer to http://infocenter.nordicsemi.com/pdf/nRF52840_Rev_1_Errata_v1.1.pdf .  Nordic Errata 202 means no external current draw (from VDD pin) is allowed during power up and VDD_HV rise time (to 3V) is below 1mS. 

For either option, if you use USB interface then the BL654 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL654 VBUS pin, you MUST externally fit a 4.7uF to ground.

BL654 powering options

Power Supply Option Notes

Low Power Modes

The BL654 has three power modes: Run, Standby Doze, and Deep Sleep.

The module is placed automatically in Standby Doze if there are no pending events (when WAITEVENT statement is encountered within a customer’s smartBASIC script). The module wakes from Standby Doze via any interrupt (such as a received character on the UART Rx line). If the module receives a UART character from either the external UART or the radio, it wakes up.

Deep sleep is the lowest power mode. Once awakened, the system goes through a system reset.

For different Nordic power modes using the Nordic SDK, refer to Nordic infocenter.nordicsemi.com.

Clocks and Timers

Clocks

The integrated high accuracy 32 MHz (±10 ppm) crystal oscillator helps with radio operation and reducing power consumption in the active modes.

The integrated on-chip 32.768 kHz LFRC oscillator (±500 ppm) provides protocol timing and helps with radio power consumption in the system StandByDoze and Deep Sleep modes by reducing the time that the RX window needs to be open.  

To keep the on-chip 32.768 kHz LFRC oscillator within ±500 ppm (which is needed to run the BLE stack) accuracy, RC oscillator needs to be calibrated (which takes 33 mS) regularly. The default calibration interval is eight seconds which is enough to keep within ±500 ppm. The calibration interval ranges from 0.25 seconds to 31.75 seconds (in multiples of 0.25 seconds) and configurable via firmware.

Timers

When using smartBASIC, the timer subsystem enables applications to be written which allow future events to be generated based on timeouts.

• Regular Timer – There are eight built-in timers (regular timers) derived from a single RTC clock which are controlled solely by smart BASIC functions. The resolution of the regular timer is 976 microseconds.
• Tick Timer – A 31-bit free running counter that increments every (1) millisecond. The resolution of this counter is 488 microseconds.

Refer to the smart BASIC User Guide available from the Ezurio BL654 product page. For timer utilization when using the Nordic SDK, refer to http://infocenter.nordicsemi.com/index.jsp

Hardware Architecture

Block Diagrams

Pin-Out / Package Layout

Mechanical Details

BL654 Mechanical Details

Development Kit Schematics can be found in the software downloads tab of the BL654 product page – https://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series-bluetooth-module-nfc

USB BLE Dongle Mechanical Details

Pin Definitions & Functionality

Pin Definition Notes

Electrical Characteristics

Absolute Maximum Ratings

Absolute maximum ratings for supply voltage and voltages on digital and analogue pins of the module are listed below; exceeding these values causes permanent damage.

Maximum current ratings

Maximum Ratings Notes

Recommended Operating Conditions

Power Supply Operating Parameters

Recommended Power Supply Operating Parameter Notes

Signal Levels and Interface Specs

Signal Levels for Inferface, SIO

Signal Levels Notes:

SIO Pin Alternative Function AIN (ADC) Specification

Recommended Operating Parameters Notes

Power Management & Consumption

Power Consumption

Data at VDD of 3.3 V with internal (to chipset) LDO ON or with internal (to chipset) DCDC ON (see Power Consumption Note 1) and 25ºC.

Peripheral Block Power Consumption

The values below are calculated for a typical operating voltage of 3V.

UART Power Consumption

SPI Power Consumption

I2C Power Consumption

ADC Power Consumption

RF, Antenna, and Wireless Details

451-00001 On-Board PCB Antenna Characteristics

The 451-00001 on-board PCB trace monopole antenna radiated performance depends on the host PCB layout.

The BL654 development board was used for BL654 development and the 451-00001 PCB antenna performance evaluation. To obtain similar performance, follow guidelines in section PCB Layout on Host PCB for the 451-00001 to allow the on-board PCB antenna to radiate and reduce proximity effects due to nearby host PCB GND copper or metal covers.

 2402MHz Radiated Performance

EIRP Azimuth Cut

3D Plots:

2440MHz Radiated Performance

EIRP Azimuth Cut

3D Plots:

2480MHz Radiated Performance

EIRP Azimuth Cut

3D Plots:

451-00001 Return Loss Measurement

Integration Guidelines

Circuit

The BL654 is easy to integrate, requiring no external components on your board apart from those which you require for development and in your end application.

The following are suggestions for your design for the best performance and functionality.

Checklist (for Schematic):

• BL654 power supply options:
  Option 1 – Normal voltage power supply mode entered when the external supply voltage is connected to both the VDD and VDDH pins (so that VDD equals VDD_HV).  Connect external supply within range 1.7V to 3.6V range to BL654 VDD and VDD_HV pins. 
  OR
  Option 2 – High voltage mode power supply mode (using BL654 VDD_HV pin) entered when the external supply voltage in ONLY connected to the VDDH pin and the VDD pin is not connected to any external voltage supply.  Connect external supply within range 2.5V to 5.5V range to BL654 VDD_HV pin. BL654 VDD pin left unconnected.                                    
  Nordic Errata 197 and 202 related to the use of VDD_HV DCDC convertor, for details refer to http://infocenter.nordicsemi.com/pdf/nRF52840_Rev_1_Errata_v1.1.pdf.  Nordic Errata 202 means no external current draw (from VDD pin) is allowed during power up and VDD_HV rise time (to 3V) is below 1mS. 
  For either option, if you use USB interface then the BL654 VBUS pin must be connected to external supply within the range 4.35V to 5.5V. When using the BL654 VBUS pin, you MUST externally fit a 4.7uF to ground.
  External power source should be within the operating range, rise time and noise/ripple specification of the BL654. Add decoupling capacitors for filtering the external source. Power-on reset circuitry within BL654 series module incorporates brown-out detector, thus simplifying your power supply design. Upon application of power, the internal power-on reset ensures that the module starts correctly.
• VDD and coin-cell operation
  With a built-in DCDC (operating range 1.7V to 3.6V), that reduces the peak current required from a coin-cell, making it easier to use with a coin-cell.
• AIN (ADC) and SIO pin IO voltage levels
  BL654 SIO voltage levels are at VDD. Ensure input voltage levels into SIO pins are at VDD also (if VDD source is a battery whose voltage will drop). Ensure ADC pin maximum input voltage for damage is not violated. 
• AIN (ADC) impedance and external voltage divider setup
  If you need to measure with ADC a voltage higher than 3.6V, you can connect a high impedance voltage divider to lower the voltage to the ADC input pin.
• JTAG
  This is REQUIRED as Nordic SDK applications can only be loaded using the JTAG (smartBASIC firmware can be loaded using the JTAG as well as the UART).
  Ezurio recommends you use JTAG (2-wire interface) to handle future BL654 module firmware upgrades. You MUST wire out the JTAG (2-wire interface) on your host design (see Figure 7, where four lines should be wired out, namely SWDIO, SWDCLK, GND and VCC). Firmware upgrades can still be performed over the BL654 UART interface, but this is slower (60 seconds using UART vs. 10 seconds when using JTAG) than using the BL654 JTAG (2-wire interface).
  JTAG may be used if you intend to use Flash Cloning during production to load smartBASIC scripts.
• UART
  Required for loading your smartBASIC application script during development (or for subsequent firmware upgrades (except JTAG for FW upgrades and/or Flash Cloning of the smartBASIC application script). Add connector to allow interfacing with UART via PC (UART–RS232 or UART-USB).
• UART_RX and UART_CTS
  SIO_08 (alternative function UART_RX) is an input, set with internal weak pull-up (in firmware). The pull-up prevents the module from going into deep sleep when UART_RX line is idling.
  SIO_07 (alternative function UART_CTS) is an input, set with internal weak pull-down (in firmware). This pull-down ensures the default state of the UART_CTS will be asserted which means can send data out of the UART_TX line. Ezurio recommends that UART_CTS be connected. 

• nAutoRUN pin and operating mode selection
  nAutoRUN pin needs to be externally held high or low to select between the two BL654 operating modes at power-up:

  • Self-contained Run mode (nAutoRUN pin held at 0V).
  • Interactive / development mode (nAutoRUN pin held at VDD).
    Make provision to allow operation in the required mode. Add jumper to allow nAutoRUN pin to be held high or low (BL654 has internal 13K pull-down by default) OR driven by host GPIO.
• I2C
  It is essential to remember that pull-up resistors on both I2C_SCL and I2C_SDA lines are not provided in the BL654 module and MUST be provided external to the module as per I2C standard.
• SPI
  Implement SPI chip select using any unused SIO pin within your smartBASIC application script or Nordic application then SPI_CS is controlled from the software application allowing multi-dropping.
• SIO pin direction
  BL654 modules shipped from production with smart BASIC FW, all SIO pins (with default function of DIO) are mostly digital inputs (see Pin Definitions Table2). Remember to change the direction SIO pin (in your smartBASIC application script) if that particular pin is wired to a device that expects to be driven by the BL654 SIO pin configured as an output. Also, these SIO pins have the internal pull-up or pull-down resistor-enabled by default in firmware (see Pin Definitions Table 2). This was done to avoid floating inputs, which can cause current consumption in low power modes (e.g. StandbyDoze) to drift with time. You can disable the PULL-UP or Pull-down through their smartBASIC application.
  Note: Internal pull-up, pull down will take current from VDD.
• SIO_02 pin and OTA smartBASIC application download feature 
  SIO_02 is an input, set with internal pull-down (in FW). Refer to latest firmware release documentation on how SIO_02 is used for Over the Air smartBASIC application download feature. The SIO_02 pin must be pulled high externally to enable the feature. Decide if this feature is required in production. When SIO_02 is high, ensure nAutoRun is NOT high at same time; otherwise you cannot load the smartBASIC application script.

• NFC antenna connector
  To make use of the Ezurio flexi-PCB NFC antenna, fit connector:

  • Description – FFC/FPC Connector, Right Angle, SMD/90d, Dual Contact,1.2 mm Mated Height
  • Manufacturer – Molex
  • Manufacturers Part number – 512810594
  • Add tuning capacitors of 300 pF on NFC1 pin to GND and 300 pF on NFC2 pins to GND if the PCB track length is similar as development board.
• nRESET pin (active low)
  Hardware reset. Wire out to push button or drive by host.
  By default module is out of reset when power applied to VCC pins.
• Optional External 32.768kHz crystal
  If the optional external 32.768kHz crystal is needed then use a crystal that meets specification and add load capacitors whose values should be tuned to meet all specification for frequency and oscillation margin.
• SIO_38 special function pin
  This is for future use by Ezurio.  It is currently a Do Not Connect pin if using the smartBASIC FW. 

PCB Layout

PCB Layout on Host PCB - General

Checklist (for PCB):

• MUST locate BL654 module close to the edge of PCB (mandatory for the 451-00001 for on-board PCB trace antenna to radiate properly).
• Use solid GND plane on inner layer (for best EMC and RF performance).
• All module GND pins MUST be connected to host PCB GND.
• Place GND vias close to module GND pads as possible.
• Unused PCB area on surface layer can flooded with copper but place GND vias regularly to connect the copper flood to the inner GND plane. If GND flood copper is on the bottom of the module, then connect it with GND vias to the inner GND plane.
• Route traces to avoid noise being picked up on VDD, VDDH, VBUS supply and AIN (analogue) and SIO (digital) traces.
• Ensure no exposed copper is on the underside of the module (refer to land pattern of BL654 development board).

PCB Layout on Host PCB for the 451-00001

Host PCB Land Pattern and Antenna Keep-Out for the 451-00001 Notes

Antenna Keep-Out on Host PCB

The 451-00001 has an integrated PCB trace antenna and its performance is sensitive to host PCB. It is critical to locate the 451-00001 on the edge of the host PCB (or corner) to allow the antenna to radiate properly. Refer to guidelines in section PCB land pattern and antenna keep-out area for the 451-00001. Some of those guidelines repeated below.

• Ensure there is no copper in the antenna keep-out area on any layers of the host PCB. Keep all mounting hardware and metal clear of the area to allow proper antenna radiation.
• For best antenna performance, place the 451-00001 module on the edge of the host PCB, preferably in the edge center.
• The BL654 development board has the 451-00001 module on the edge of the board (not in the corner). The antenna keep-out area is defined by the BL654 development board which was used for module development and antenna performance evaluation is shown in Figure 14, where the antenna keep-out area is ~5 mm wide, ~39.95 mm long; with PCB dielectric (no copper) height ~1 mm sitting under the 451-00001 PCB trace antenna.
• The 451-00001 PCB trace antenna is tuned when the 451-00001 is sitting on development board (host PCB) with size of 125 mm x 85 mm x 1mm.
• A different host PCB thickness dielectric will have small effect on antenna.
• The antenna-keep-out defined in the Host PCB Land Pattern and Antenna Keep-out for the 451-00001 section.

• Host PCB land pattern and antenna keep-out for the BL654 applies when the 451-00001 is placed in the edge of the host PCB preferably in the edge center
  

  

Antenna Keep-Out Notes:

Antenna Keep-Out and Proximity to Metal or Plastic

Checklist (for metal /plastic enclosure):

• Minimum safe distance for metals without seriously compromising the antenna (tuning) is 40 mm top/bottom and 30 mm left or right.
• Metal close to the 451-00001 PCB trace monopole antenna (bottom, top, left, right, any direction) will have degradation on the antenna performance. The amount of that degradation is entirely system dependent, meaning you will need to perform some testing with your host application.
• Any metal closer than 20 mm will begin to significantly degrade performance (S11, gain, radiation efficiency). 
• It is best that you test the range with a mock-up (or actual prototype) of the product to assess effects of enclosure height (and materials, whether metal or plastic).

External Antenna Integration with the 451-00002

Please refer to the regulatory sections for FCC, ISED, EU, and Japan for details of use of BL654-with external antennas in each regulatory region.

The BL654 family has been designed to operate with the below external antennas (with a maximum gain of
2.0 dBi). The required antenna impedance is 50 ohms. See Table 27. External antennas improve radiation efficiency.

External antennas for the BL654

Application Note for Surface Mount Modules

Introduction

Ezurio surface mount modules are designed to conform to all major manufacturing guidelines. This application note is intended to provide additional guidance beyond the information that is presented in the User Manual. This Application Note is considered a living document and will be updated as new information is presented.

The modules are designed to meet the needs of several commercial and industrial applications. They are easy to manufacture and conform to current automated manufacturing processes.

Shipping

Tape and Reel Packaging

There are 1,000 x BL654 modules taped in a reel (and packaged in a pizza box) and five boxes per carton (5000 modules per carton). Reel, boxes, and carton are labeled with the appropriate labels. See Carton Contents for more information.

Carton Contents

The following are the contents of the carton shipped for the BL654 modules.

Module Orientation in Cavity

Labeling

The following package label is located on the box:

The following package label is located on the adjacent sides of the master carton:

Reflow Parameters

Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained during storage and shipment. If directed to bake units on the card, see Table 28 and follow instructions specified by IPC/JEDEC J-STD-033. A copy of this standard is available from the JEDEC website: http://www.jedec.org/sites/default/files/docs/jstd033b01.pdf

Any modules not manufactured before exceeding their floor life should be re-packaged with fresh desiccate and a new humidity indicator card. Floor life for MSL (Moisture Sensitivity Level) four devices is 72 hours in ambient environment £30°C/60%RH.

Recommended baking times and temperatures

Ezurio surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB. Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven temperatures during reflow meet the requirements of the solder paste. Ezurio surface mount modules conform to J-STD-020D1 standards for reflow temperatures.

Temperatures should not exceed the minimums or maximums presented below.

Recommended maximum and minimum temperatures

Environmental and Reliability

Environmental Requirements

Reliability Tests

The BL654 module went through the below reliability tests and passed.  

Before and after the testing, visual inspection showed no physical defect on samples.

After Vibration test and Mechanical Shock testing, the samples were functionally tested, and all samples functioned as normal.  Then after Thermal shock test, the samples were functionally tested, and all samples functioned as normal.

Regulatory, Qualification & Certifications

Regulatory Approvals

The BL654 holds current certifications in the following countries:

Bluetooth SIG Qualification

The Bluetooth Qualification Process promotes global product interoperability and reinforces the strength of the Bluetooth® brand and ecosystem to the benefit of all Bluetooth SIG members. The Bluetooth Qualification Process helps member companies ensure their products that incorporate Bluetooth technology comply with the Bluetooth Patent & Copyright License Agreement and the Bluetooth Trademark License Agreement (collectively, the Bluetooth License Agreement) and Bluetooth Specifications.

The Bluetooth Qualification Process is defined by the Qualification Program Reference Document (QPRD) v3.

To demonstrate that a product complies with the Bluetooth Specification(s), each member must for each of its products:

• Identify the product, the design included in the product, the Bluetooth Specifications that the design implements, and the features of each implemented specification
• Complete the Bluetooth Qualification Process by submitting the required documentation for the product under a user account belonging to your company

The Bluetooth Qualification Process consists of the phases shown below:

To complete the Qualification Process the company developing a Bluetooth End Product shall be a member of the Bluetooth SIG.  To start the application please use the following link: Apply for Adopter Membership

Scope

This guide is intended to provide guidance on the Bluetooth Qualification Process for End Products that reference multiple existing designs, that have not been modified, (refer to Section 3.2.2.1 of the Qualification Program Reference Document v3).

For a Product that includes a new Design created by combining two or more unmodified designs that have DNs or QDIDs into one of the permitted combinations in Table 3.1 of the QPRDv3, a Member must also provide the following information:

• DNs or QDIDs for Designs included in the new Design
• The desired Core Configuration of the new Design (if applicable, see Table 3.1 below)
• The active TCRL Package version used for checking the applicable Core Configuration (including transport compatibility) and evaluating test requirements

Any included Design must not implement any Layers using withdrawn specification(s).

When creating a new Design using Option 2a, the Inter-Layer Dependency (ILD) between Layers included in the Design will be checked based on the latest TCRL Package version used among the included Designs.

For the purposes of this document, it is assumed that the member is combining unmodified Core-Controller Configuration and Core-Host Configuration designs, to complete a Core-Complete Configuration.

Qualification Steps When Referencing multiple existing designs, (unmodified) – Option 2a in the QPRDv3

For this qualification option, follow these steps:

1. To start a listing, go to: https://qualification.bluetooth.com/
2. Select Start the Bluetooth Qualification Process.

3. Product Details to be entered:

   1. Project Name (this can be the product name or the Bluetooth Design name).
   2. Product Description
   3. Model Number
   4. Product Publication Date (the product publication date may not be later than 90 days after submission)
   5. Product Website (optional)
   6. Internal Visibility (this will define if the product will be visible to other users prior to publication)
   7. If you have multiple End Products to list then you can select ‘Import Multiple Products’, firstly downloading and completing the template, then by ‘Upload Product List’.  This will populate Qualification Workspace with all your products.

4. Specify the Design:

   1. Do you include any existing Design(s) in your Product? Answer Yes, I do.
   2. Enter the multiple DNs or QDIDs used in your, (for Option 2a two or more DNs or QDIDs must be referenced)
   3. Select ‘I’m finished entering DN’s
   4. Once the DNs or QDIDs are selected they will appear on the left-hand side, indicating the layers covered by the design (should show Core-Controller and Core Host Layers covered).
   5. What do you want to do next? Answer, ‘Combine unmodified Designs’.
   6. The Qualification Workspace Tool will indicate that a new Design will be created and what type of Core-Complete configuration is selected.
   7. An active TCRL will be selected for the design.
   8. Perform the Consistency Check, which should result in no inconsistencies
   9. If there are any inconsistencies these will need to be resolved before proceeding
   10. Save and go to Test Plan and Documentation

5. Test Plan and Documentation

   1. As no modifications have been made to the combined designs the tool should report the following message:
      ‘No test plan has been generated for your new Design. Test declarations and test reports do not need to be submitted. You can continue to the next step.’
   2. Save and go to Product Qualification fee

6. Product Qualification Fee:

   1. It’s important to make sure a Prepaid Product Qualification fee is available as it is required at this stage to complete the Qualification Process.
   2. Prepaid Product Qualification Fee’s will appear in the available list so select one for the listing.
   3. If one is not available select ‘Pay Product Qualification Fee’, payment can be done immediately via credit card, or you can pay via Invoice.  Payment via credit will release the number immediately, if paying via invoice the number will not be released until the invoice is paid.
   4. Once you have selected the Prepaid Qualification Fee, select ‘Save and go to Submission’

7. Submission:

   1. Some automatic checks occur to ensure all submission requirements are complete.
   2. To complete the listing any errors must be corrected
   3. Once you have confirmed all design information is correct, tick all of the three check boxes and add your name to the signature page.
   4. Now select ‘Complete the Submission’.
   5. You will be asked a final time to confirm you want to proceed with the submission, select ‘Complete the Submission’.
   6. Qualification Workspace will confirm the submission has been submitted.  The Bluetooth SIG will email confirmation once the submission has been accepted, (normally this takes 1 working day).

8. Download Product and Design Details (SDoC):

   1. You can now download a copy of the confirmed listing from the design listing page and save a copy in your Compliance Folder

For further information, please refer to the following webpage:

https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/

Example Design Combinations

The following gives an example of a design possible under option 2a:

Ezurio Controller Subsystem + Nordic nRF Connect SDK Host Subsystem (Ezurio BL654 based design)

Qualify More Products

If you develop further products based on the same design in the future, it is possible to add them free of charge.  The new product must not modify the existing design i.e add ICS functionality, otherwise a new design listing will be required.

To add more products to your design, select ‘Manage Submitted Products’ in the Getting Started page, Actions, Qualify More Products.  The tool will take you through the updating process.

Ordering Information