Nitrogen95 SMARC (Preliminary)

  1. Scope
  2. Introduction
    1. Overview
    2. General Description
  3. Specification Summary
    1. Processor / SoC / Chipset
    2. Interfaces
    3. Power
    4. Mechanical
    5. Software
    6. Environmental
    7. Certifications
    8. Development
    9. Warranty
  4. Functional Descriptions
    1. Power-Up Sequence and Timing
  5. Hardware Architecture
    1. Block Diagrams
    2. Pin-Out and Pinmux Table
    3. Mechanical Drawings
    4. Heatsink
  6. Electrical Characteristics
    1. Absolute Maximum Ratings
    2. Recommended Operating Conditions
    3. DC Current Consumption
  7. Power Management & Consumption
    1. DC Power Tree
    2. Power Modes
  8. Environmental and Reliability
    1. Environmental Requirements
  9. Regulatory, Qualification & Certifications
    1. Regulatory Approvals
  10. Ordering Information
  11. Legacy - Revision History
Nitrogen95 SMARCEZSMI-959-0816-00117-2EZSMI-959-0816-00158-2EZSMI-959-0816-00158-2-K2EZSMI-959-0816-00158-2-KC

Scope

This document describes key hardware aspects of Ezurio’s Nitrogen95 SMARC system-on-module which is based on the i.MX 95 processor family and the Sona family Wi-Fi/BT combo radio. Data in this document is drawn from several sources and includes information found in the documentation for NXP’s i.MX 95 and our Sona family.

Note: Information in this document is subject to change. Contact us for the most updated version of this document.

Introduction

Overview

This document describes key hardware aspects of the Nitrogen95 SMARC. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the Nitrogen95 SMARC, visit:

https://www.ezurio.com/nitrogen95-smarc

General Description

The Nitrogen95 SMARC is an integrated platform solution with up to six Arm Cortex A55 cores, a high-performance real-time domain with Arm Cortex M7, and low-power/safety domain with Arm Cortex M33, each able to access interfaces including CAN-FD, 10GbE networking, PCIe Gen 3 x1 interfaces, and accelerators such as V2X, ISP, and VPU. The i.MX 95 family enables machine vision through its integrated eIQ Neutron NPU as part of a vision processing pipeline for use with multiple camera sensors or network attached smart cameras.

Additionally, it offers the latest high-speed interfaces for connectivity and fast data transfer with 2x PCIe Gen 3.0, 1x USB 2.0 Type C, 2x USB 3.0, 1x USB 2.0, 3x SD/SDIO 3.01, 2x 1 Gbps Ethernet with TSN, 1x 10 Gbps Ethernet with TSN, IEEE 1588, EEE, in addition to 2x CAN-FD interfaces. The memory interfaces supported are 16-bit LPDDR5X and eMMC 5.1.

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