Nitrogen95 SMARC (Preliminary)

Scope

This document describes key hardware aspects of Ezurio’s Nitrogen95 SMARC system-on-module which is based on the i.MX 95 processor family and the Sona family Wi-Fi/BT combo radio. Data in this document is drawn from several sources and includes information found in the documentation for NXP’s i.MX 95 and our Sona family.

Introduction

Overview

This document describes key hardware aspects of the Nitrogen95 SMARC. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the Nitrogen95 SMARC, visit:

https://www.ezurio.com/nitrogen95-smarc

General Description

The Nitrogen95 SMARC is an integrated platform solution with up to six Arm Cortex A55 cores, a high-performance real-time domain with Arm Cortex M7, and low-power/safety domain with Arm Cortex M33, each able to access interfaces including CAN-FD, 10GbE networking, PCIe Gen 3 x1 interfaces, and accelerators such as V2X, ISP, and VPU. The i.MX 95 family enables machine vision through its integrated eIQ Neutron NPU as part of a vision processing pipeline for use with multiple camera sensors or network attached smart cameras.

Additionally, it offers the latest high-speed interfaces for connectivity and fast data transfer with 2x PCIe Gen 3.0, 1x USB 2.0 Type C, 2x USB 3.0, 1x USB 2.0, 3x SD/SDIO 3.01, 2x 1 Gbps Ethernet with TSN, 1x 10 Gbps Ethernet with TSN, IEEE 1588, EEE, in addition to 2x CAN-FD interfaces. The memory interfaces supported are 16-bit LPDDR5X and eMMC 5.1.

The module also includes 2x 4-lane MIPI-CSI camera and optional ISP interfaces capable of supporting 1x 4Kp60, 2x 4Kp30, 4x 1080p60, or 8x 1080p30.

The i.MX 95 family implements security via NXP’s EdgeLock® secure enclave, a preconfigured, self-managed and autonomous security subsystem. EdgeLock eases the complexity of implementing robust, device-wide security intelligence for IoT applications through autonomous management of critical security functions, such as root of trust, run-time attestation, trust provisioning, secure boot, key management and cryptographic services while also simplifying the path to industry-standard security certifications.

The Nitrogen95 SMARC includes the Sona family which is pre-calibrated and integrates the complete transmit/receive RF paths including bandpass filter, diplexer, switches, reference crystal oscillator, and power management units (PMU). Three RF connectors (MHF4) on the module provide the most flexibility for antenna selection, installation and performance. Two ports for WLAN and one dedicated for Bluetooth. Several high-performance antennas are certified with the Sona family onboard the Nitrogen95 SMARC.

The Nitrogen95 SMARC has several product SKUs providing different eMMC and LPDDR5 memory configurations, see Ordering Information section.

This datasheet is subject to change. Please contact Ezurio for further information.

Specification Summary

Processor / SoC / Chipset

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Functional Descriptions

Power-Up Sequence and Timing

Boot Mode

The Nitrogen95 SMARC module contains a switch (SW1) connected to BOOT_MODE0 thus allowing to switch from internal fuses boot (eMMC by default) to USB serial downloader.

The other boot mode signals (BOOT_MODE[1-3]) are not exposed to the carrier as used for different functions (UART/I2S). But a BOM change can select a custom boot mode (see resistors R128 to R135).

This allows more combinations as shown below.

Boot mode combinations

Hardware Architecture

Block Diagrams

The figure below shows the block diagram of the Nitrogen95 SMARC which contains the NXP i.MX 95 processor, PMIC (PF09/PF53*2) and the Sona family Wi-Fi/BT combo.

Detailed connections between a Sona module and the i.MX 95 are detailed below.

Sona IF573 to i.MX 95 Connections

Pin-Out and Pinmux Table

The following table lists the pin multiplexing (PIN-MUX) of the Nitrogen95 SMARC.

PO = Power Output, PI = Power Input, DI = Digital Input, DO = Digital Output, DIO = Bi-directional Digital Port, GND = Ground

NXP process has configurable internal Pull-up (PU) and pull-down (PD) resistor whose values are listed below. During a reset condition, the PU and PD state are pre-defined and cannot be changed.

Resistor characteristics

Pin configuration for the i.MX is achieved using a suite of evaluation and configuration tools that assists users from initial evaluation to production software development. Users can download the tool from the NXP website: https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX?tab=Design_Tools_Tab

Pinout table for Nitrogen95 SMARC edge connector (J2)

Mechanical Drawings

Module dimensions of the Nitrogen95 SMARC are 82 x 50 mm. Detail drawings are shown below.

Electrical Characteristics

Absolute Maximum Ratings

The following table summarizes the absolute maximum ratings for the Nitrogen95 SMARC product series. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended.

Absolute maximum ratings

Recommended Operating Conditions

The following table lists the recommended operating conditions for the Nitrogen95 SMARC product series.

Recommended Operating Conditions

DC Current Consumption

Several power saving modes are available and are listed below.

Typical current consumption

Power Management & Consumption

DC Power Tree

The Nitrogen95 SMARC requires a primary 5V input (VSYS) as its main power source. This inputs powers the on-module NXP PPF0900AVNA1ES power management IC (PMIC), which generates all necessary voltages for the module’s components. Additional power management is provided by the PPF5302AVNAAEP and PPF5301AVNABEP PMICs.

Power Modes

NXP PPF0900AVNA1ES has ten power modes: ULPOFF, LPOFF, DBGOFF, Self-Test, PWRUP, RUN, STANDBY, PWRDN, Fail-Safe and Deep Fail Safe. Below figure shows the state transition diagram showing the conditions to enter and exit each state.

• ULPOFF Mode:
  The ULPOFF (Ultra-low power off) state is provided to allow the PMIC to remain in an OFF condition with minimum functional operation, minimum quiescent current and the ability to wake-up if the PWRON pin is asserted high.
• LPOFF Mode:
  During the LPOFF (Low power off) state, only the VAON regulator can be enabled if it is configured as an always-on supply via the OTP configuration. All other system regulators will remain disabled until the power-up sequence is started.
• DBGOFF Mode:
  During normal system operation, the DBGOFF (Debug Off) state will be a transitory state between a power-on event and the Power-up sequence. It serves as the gating state to ensure the PMIC is ready to start a power up sequence and allow synchronization of two or more PMICs providing full power architecture to a complex system.

• Self-Test Mode:
  In devices with a high safety integrity level (ASIL/SIL) the Self-test routine is performed when the state machine transitions out of the LPOFF state. During the self-test, the PF09 performs a startup self-check routine to verify the integrity of the system:

  • The high-speed oscillator circuit is operating within a maximum of 6% tolerance.
  • The output of both the voltage generation bandgap and the monitoring bandgap are not drifting apart from each other.
  • A CRC is performed on the Mirror Registers during the self-test routine, to ensure the integrity of the OTP registers before powering up.
  • Analog built-in test on all voltage monitors and Safety I/Os is performed.
• PWRUP Mode:
  The PF09 provides a highly configurable power-up sequence to enable the system regulators and general-purpose IO pins in a specific order and timing during the power-up state. The default configuration for the power-up sequence is loaded from the OTP registers to ensure the system always turns on with the correct configuration every power-up cycle as defined on each specific part number.
• RUN Mode:
  If the Power-up sequence is completed successfully, the state machine transitions directly into the RUN state. The RUN State is a full featured state providing full functionality and monitoring as described in this document.
• STANDBY Mode:
  The STANDBY state is a secondary functional state with programable functionality to prioritize either system monitoring or low power operation.

• PWRDN Mode:
  Three types of events may lead to the Power-down sequence.

  • TURNOFF: Non-faulty Turn off events move directly into the corresponding Low power state as soon as the power down sequence is finalized.
  • FAULT: Turn off events due to a PMIC fault will move into the Fail-Safe transition as soon as the power down sequence is finalized.
  • RESET: A RESET state is provided to allow the system to refresh the configuration without looping through a full power cycle.
• Fail-Safe Mode:
  During the Fail-safe transition, the VAON remains enabled if it is configured as an Always-on regulator. All system regulators will remain disabled until the next power-up sequence.
• Deep Fail Safe Mode:
  The DFS state is intended to work as a temporary lockdown state upon a cyclic critical failure condition. Since the system may land in the DFS state and remain there indefinitely, the DFS state is designed to consume as little current as possible, with just the minimum blocks enabled to perform the operations defined in this state.

Environmental and Reliability

Environmental Requirements

Required Storage Conditions

• Prior to Opening the Dry Packing
  The following are required storage conditions prior to opening the dry packing:

  • Normal temperature: 5~40℃
  • Normal humidity: 80% (Relative humidity) or less
  • Storage period: One year or less

Regulatory, Qualification & Certifications

Regulatory Approvals

Radio certifications for SOMs with wireless options are held under the specific wireless module listings:

Ordering Information

Legacy - Revision History