BL54L10 and BL54L15 Series

Introduction

Overview

This document describes key hardware aspects of the BL54L15 and BL54L10. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the BL54L15 and BL54L10, visit:

https://www.ezurio.com/bl54l15

https://www.ezurio.com/bl54l10-series

General Description

Experience a new pinnacle of performance, efficiency, and security with our new BL54L15 and BL54L10 series, built on Nordic Semiconductor's powerful nRF54L QFN silicon. Elevating what you know and love from the nRF52 series, this next generation redefines Bluetooth LE and 802.15.4 solutions. Unleashing enhanced processing power, expanded memory, and innovative peripherals, the BL54L15 is the ultimate choice for low power connectivity.

Powered by Nordic's nRF54L15 and nRF54L10 SoC, our compact BL54L15 and BL54L10 modules deliver secure and robust Bluetooth LE and 802.15.4 with flexible programming via Nordic’s nRF Connect SDK or Ezurio Canvas Software Suite.

Featuring a 128MHz ARM Cortex M33 and 128MHz RISC-V coprocessor, supported by 1.5 MB non-volatile memory and 256 KB RAM for BL54L15, 1.0 MB non-volatile memory and 192 KB RAM for BL54L10, the BL54L15 and BL54L10 modules offer double the processing power (vs prior BL654 – nRF52840). The BL54L15 / L10 series brings out all nRF54L15/ L10 hardware features and capabilities including up to +7 dBm transmit power, 1.7V – 3.6V supply considerations, and NFC A-Tag implementation.

It’s further enhanced with state-of-the-art security and is designed for PSA Certified level 3 and supports services such as Secure Boot, Secure Firmware Update, Secure Storage plus protection from physical attacks.

This datasheet is subject to change. Please contact Ezurio for further information.

Application Areas

• Building Automation
• Security
• Medical Peripherals
• Industrial Sensors

Features & Benefits

The BL54L15 device features and benefits are described below.

• Nordic nRF54L15/ nRF54L10 – 6x6 mm QFN48 with 31 GPIOs utilized.
• Multi-protocol support: Bluetooth LE, 802.15.4 (Thread & Matter)
• Cortex M33 processor core: 128 MHz ARM Cortex M33
• RISC-V co-processor core: 128 MHz VPR

• Memory:

  • 1.5MB non-volatile memory, 256 KB RAM for BL54L15
  • 1.0MB non-volatile memory, 192 KB RAM for BL54L10
• High Speed Peripherals: - HS-SPI/UART, software defined peripherals on 128 MHz VPR, GPIO - 1x 64 MHz Port, 1.7 – 3.6V, 11 GPIOs
• Low Leakage Peripherals: 2x QDEC, 7x Timer, Global RTC, 2x WDT, NFC A-Tag, TEMP, I2S, COMP, 3x PWM, LPCOMP, 14-bit 8CH ADC, 5x TWI/SPI/UART, GPIO (2x 16 MHz Port (P0, P1), 20 GPIO’s, 1.7-3.6V, 31 GPIO)
• Antenna choice – integrated pre-certified PCB Trace antenna or external antenna support via MHF4 connector
• Ultra-small footprint (14 mm x 10 mm x 1.6 mm)
• Extended Industrial Temperature Rating (-40° to +105 °C)

Specification Summary

Processor / SoC / Chipset

Bluetooth

NFC

Radio Performance

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Functional Descriptions

Programming & Firmware

The BL54L15/BL54L10 module is shipped from Ezurio manufacturing facilities with no firmware programmed.

BL54L15 BL54L10 Firmware Options

Firmware for use with the BL54L15/BL54L10 can be divided into the following types.

• Bootloader – This is the application that resides on the Application Core used to perform firmware updates of the Application and FLPR cores.

The MCU Boot or Trusted Firmware M Bootloaders are recommended to be used as the basis for the BL54L15 Bootloader functionality.

• Application – This is the main application running on the Application core. In interfaces with the integrated radio stack(s) and provides supplementary functionality in addition to the time critical activities performed for radio activity.
• Software Defined Peripheral – This is the application running on the RISC-V FLPR core.

Clocks

HFXO - 32MHz crystal oscillator and nRF54L15/nRF54L10 internal load capacitor mandatory setting

The BL54L15/BL54L10 module contains the 32 MHz crystal, but the load capacitors to create 32MHz crystal oscillator circuit are inside the nRF54L15/nRF54L10 chipset. Customer can set the internal nRF54L15/nRF54L10 capacitors from 4 pF to 17 pF in 0.25pF if needed or use default value without changing.

The 32 MHz crystal inside the BL54L15/BL54L10 module is a high accuracy crystal (±15 ppm at room temperature) that helps with radio operation and reducing power consumption in the active modes.

LFCLK – Low Frequency clock source

There are four possibilities (see figure 3) for the low frequency clock (LFCLK) and options are:

LFRC (32.768kHz RC oscillator):  The Internal 32.768 kHz RC oscillator (LFRC) is fully embedded in nRF54L15/nRF54L10 (and does not require additional external components) with an accuracy ±250 ppm (after calibration of LFRC at least every eight seconds using the HFXO as a reference oscillator).

LFXO (32.768kHz crystal oscillator):  For higher LFCLK accuracy (greater than ±250ppm accuracy is required), the low frequency crystal oscillator (LFXO) must be used.  To use LFXO, a 32.768kHz crystal must be connected between the XL1 and XL2 pins and the load capacitance between each crustal terminal and ground.   Optionally internal (to nRF54L15/nRF54L10) capacitor of maximum 18 pF in 0.5 pF steps are provided on pins XL1 and XL2.  

Low frequency (32.768 kHz) external source:  The 32.768 kHz oscillator (LFXO) is designed to work with external sources

LFSYNTH (32.768kHz Synthesised clock) from HFCLK (LFSYNTH):  The LFCLK can be synthesised from the HFCLK source.  LFSYNTH depends on the HFCLK to run.  The accuracy of the LFCLK clock with LFSYNTH as a source assumes the accuracy of the HFCLK. If high accuracy is required, the HFCLK must generated from the HFXO.   Using the LFSYNT clock removes the requirement for an external 32.768kHz crystal but the increases the average power consumption as the HFCLK will turned on in the system.

Other Internal Clocks

Hardware Architecture

Block Diagrams

Pin-Out

Power Supply

Mechanical Drawings

3D models for BL54L15 Module, MHF4 (453-00044) and BL54L15 Module, Trace Antenna (453-00001)  on the BL54L15 product page – https://www.ezurio.com/product/bl54l15-series-bluetooth-le-80215-4-nfc

Electrical Characteristics

Absolute Maximum Ratings

Absolute maximum ratings are the extreme limits for supply voltage and voltages on digital and analogue pins of the module are listed below; exceeding these values causes permanent damage.

Recommended Operating Conditions

Power supply operating parameters

Power Management & Consumption

Power Consumption

Integration Guidelines

Host PCB Land Pattern and Antenna Keep-Out

PCB footprint - BL54L15 (DXF and Altium format) and SCH Symbol - BL54L15 (Altium format) can be found on the BL54L15 product page – https://www.ezurio.com/product/bl54l15-series-bluetooth-le-80215-4-nfc

BL54L10 use the same footprint of BL54L15.

All dimensions are in mm.

On-Board PCB Trace Antenna Characteristics

Summary of Antenna Performance

Radiated Performance

Antenna S11 Measuring Data

Software Requirements Related to Hardware

32MHz crystal internal load capacitor setting

BL54L15/ BL54L10 module contains the 32 MHz crystal but the load capacitors to create 32 MHz crystal oscillator circuit are inside the nRF54L15/ nRF54L10 chipset. Customer can set the internal nRF54L15/nRF54L10 capacitors from 4 pF to 17 pF in 0.25pF if needed, or use default value without changing.

Circuit (Overview and Checklist)

The BL54L15/ BL54L10 is easy to integrate, requiring one mandatory external 10uF capacitor on customers board and apart from that those components which customer require for development and in your end application.

The following are suggestions for your design for the best performance and functionality.

Checklist (for Schematic):

• BL54L15/ BL54L10 power supply:
  Normal voltage mode power supply mode is entered when the external supply voltage (1.7V-3.6V) is connected to both VDD_nRF pin (pin26).
  External power source should be within the operating range, rise time and noise/ripple specification of the BL54L15/ BL54L10. Add decoupling capacitors for filtering the external source. Power-on reset circuitry within BL54L15/ BL54L10 series module incorporates brown-out detector, thus simplifying your power supply design. Upon application of power, the internal power-on reset ensures that the module starts correctly.

• AIN (ADC) and GPIO pin IO voltage levels:
  BL54L15/BL54L10 GPIO voltage levels are at VDD_nRF. Ensure input voltage levels into GPIO pins are at VDD_nRF also. Ensure ADC pin maximum input voltage for damage is not violated.

• AIN (ADC) impedance and external voltage divider setup:
  If you need to measure with ADC a voltage higher than 3.6V, you can connect a high impedance voltage divider to lower the voltage to the ADC input pin.

• SWD:
  This is REQUIRED for loading firmware. MUST wire out the SWD two wire interface on host design. Five lines should be wired out, namely SWDIO, SWDCLK, nRESET, GND and VDD.

• UART and flow control (CTS, RTS):
  Required if customer requires UART.

• TWI (I2C):
  It is essential to remember that pull-up resistors on both SCL and SDA lines are required, the value as per I2C standard. nRF54L15/ nRF54L10 can provide 13K Ohms typical pull up values internally. For other values, fit external pull-up resistor on both SCL and SDA as per I2C specification to set speed. The I2C specification allows a line capacitance of 400pF.

• QSPI, High Speed SPI, High speed TWI (I2C, 1Mbps) and Trace:
  High-Speed SPI, TWI and Trace come on dedicated GPIO pins only. Other lower speed SPI and TWI can come out on any GPIO pins.
  For all high-speed signal, the printed circuit board (PCB) layout must ensure that connections are made using short PCB traces.

• GPIO pins
  If GPIO is selected as an input, ensure the input is not floating (which can cause current consumption to drive with time in low power modes (such as System ON Idle), by selecting the internal pull up or pull down.

• NFC antenna connector: To make use of the Ezurio flexi-PCB NFC antenna (part # 0600-00061), fit connector:
  Description – FFC/FPC Connector, Right Angle, SMD/90d, Dual Contact,1.2 mm Mated Height
  Manufacturer – Molex
  Manufacturers Part number – 512810594
  Add tuning capacitors of 300 pF on NFC1 pin to GND and 300 pF on NFC2 pins to GND if the PCB track length is similar as development board.

• nRESET pin (active low):
  Hardware reset. Wire out to push button or drive by host.
  By default module is out of reset when power applied to VDD_nRF pins (13K pull-up inside BL54L15/ BL54L10 (nRF54L15-QFAA/nRF54L10-QFAA)).

• Optional External 32.768kHz crystal:
  If the optional external 32.768kHz crystal is needed, then use a crystal that meets specification and add load capacitors (either inside nRF54L15-QFAA/nRF54L10-QFAA or discrete capacitors outside BL54L15/BL54L10 (nRF54L15-QFAA/nRF54L10-QFAA) whose values should be tuned to meet all specification for frequency and oscillation margin.

PCB Layout

PCB Layout on Host PCB - General

Checklist (for PCB):

• MUST locate BL54L15/ BL54L10 module close to the edge of PCB (mandatory for the 453-00001/453-00225 for on-board PCB trace antenna to radiate properly).

• Use solid GND plane on inner layer (for best EMC and RF performance).

• All module GND pins MUST be connected to host PCB GND.

• Place GND vias close to module GND pads as possible.

• Unused PCB area on surface layer can flooded with copper but place GND vias regularly to connect the copper flood to the inner GND plane. If GND flood copper is on the bottom of the module, then connect it with GND vias to the inner GND plane.

• Route traces to avoid noise being picked up on VDD_nRF supply and AIN (analogue), GPIO (digital) traces and high-speed traces.

• Ensure no exposed copper is on the underside of the module (refer to land pattern of BL54L15/BL54L10 development board).

Antenna Keep-Out on Host PCB

The 453-00001/453-00225 has an integrated PCB trace antenna and its performance is sensitive to host PCB. It is critical to locate the 453-00001/453-00225 on the edge of the host PCB (or corner) to allow the antenna to radiate properly. Refer to guidelines in section PCB land pattern and antenna keep-out area for the 453-00001/453-00225. Some of those guidelines repeated below.

• Ensure there is no copper in the antenna keep-out area on any layers of the host PCB. Keep all mounting hardware and metal clear of the area to allow proper antenna radiation.

• For best antenna performance, place the 453-00001/453-00225 module on the edge of the host PCB, preferably in the edge center.

• The BL54L15 development board (453-00001-K1) has the 453-00001 module on the edge of the board (not in the corner). The antenna keep-out area is defined by the BL54L15 development board which was used for module development and antenna performance evaluation is shown in Figure 6, where the antenna keep-out area is ~5mm wide, ~28.6mm long; with PCB dielectric (no copper) height ~1.57mm sitting under the 453-00001 PCB trace antenna module. Bl54L10 module (453-00225) please follow the same design of BL54L15.

• The 453-00001 PCB trace antenna is tuned when the 453-00001 is sitting on development board (host PCB) with size of 113 mm x 63.5 mm x 1.6mm.

• A different host PCB thickness dielectric will have small effect on antenna.

• The antenna-keep-out defined in the 8.2 Host PCB Land Pattern and Antenna Keep-out for the 453-00001 and 453-00225 section.

• Host PCB land pattern and antenna keep-out for the BL54L15/BL54L10 applies when the 453-00001/453-00225 is placed in the edge of the host PCB preferably in the edge center. Below shows an example.
  

  

Antenna Keep-out and Proximity to Metal or Plastic

Checklist (for metal /plastic enclosure):

• Minimum safe distance for metals without seriously compromising the antenna (tuning) is 40 mm top/bottom and 30 mm left or right.

• Metal close to the 453-00001/453-00225 PCB trace monopole antenna (bottom, top, left, right, any direction) will have degradation on the antenna performance. The amount of that degradation is entirely system dependent, meaning you will need to perform some testing with your host application.

• Any metal closer than 20 mm will begin to significantly degrade performance (S11, gain, radiation efficiency).

• It is best that you test the range with a mock-up (or actual prototype) of the product to assess effects of enclosure height (and materials, whether metal or plastic) and host PCB ground (GND plane size).

External Antenna Integration with BL54L15/BL54L10 MHF4 variant (453-00044/453-00226)

Please refer to the regulatory sections for FCC, ISED, CE, MIC, UKCA and RCM details of use of BL54L15 with external antennas in each regulatory region.

The BL54L15/BL54L10 family has been designed to operate with the below external antennas (with a maximum gain of
2.32 dBi). The required antenna impedance is 50 ohms. See the table below. External antennas improve radiation efficiency.

External antennas for the BL54L15/BL54L10 RF trace pin variant module (453-00044/453-00226)

Application Note for Surface Mount Modules

Introduction

Ezurio’s surface mount modules are designed to conform to all major manufacturing guidelines. This application note is intended to provide additional guidance beyond the information that is presented in the user manual. This application note is considered a living document and will be updated as new information is presented.

The modules are designed to meet the needs of several commercial and industrial applications. They are easy to manufacture and conform to current automated manufacturing processes.

Part numbers  – 453-00001R/453-00225R and 453-00044R/453-00226R are shipped as Tape / Reel, with a reel containing 1,000 pcs.

Shipping

All modules are shipped in tape and reel package and sealed in ESD Bags.

Labeling

MSL Label

Product Identifier Labels

The following labels are placed on the pizza box.

The following labels are placed on the master shipping carton.

Recommended Stencil Aperture

When soldering, the stencil thickness should be ≥ 0.1 mm.

Reflow Parameters/ Soldering

Convection reflow or IR/Convection reflow (one-time soldering or two-time soldering in air or nitrogen environment)

• Measuring point – IC package surface

• Temperature profile:
  

  
• Ramp-up: 40-130˚C. Less than 2.5˚C/sec
• Pre heat: 130-180˚C 60-120 sec, 180˚C MAX
• Ramp-up: 180-220˚C. Less than 3˚C/sec

• Peak Temperature: MAX 250˚C

  • 225˚C ~ 250˚C, 30 ~ 50 sec
• Ramp-down: Less than 3˚C/sec

Cautions when Removing the BL54L15/BL54L10 from the Platform for RMA

• Bake the platform PCBA before removing the BL54L15/BL54L10 module from the platform.
• Remove the BL54L15/BL54L10 module by using a hot air gun. This process should be carried out by a skilled technician.

Recommended conditions for one-side component platform:

• Set the hot plate at 280°C.
• Put the platform on the hot plate for 8~10 seconds.
• Remove the device from platform.

Recommended conditions for two-side components platform:

• Use two hot air guns.
• On the bottom, use a pre-heated nozzle (temp setting of 200~250°C) at a suitable distance from the platform PCB.

• On the top, apply a remove nozzle (temp setting of 330°C). Heat until device can be removed from platform PCB.

  
• Remove the residue solder under the bottom side of device. (Note: Alternate module pictured as an example)

(Not accepted for RMA)	(Accepted for RMA analysis)

• Remove and clean the residue flux as needed.

Precautions for Use

• Opening/handing/removing must be done on an anti-ESD treated workbench. All workers must also have undergone anti-ESD treatment.
• The devices should be mounted within one year of the date of delivery.
• The BL54L15/BL54L10 modules are MSL 4 rated.

Environmental and Reliability

Environmental Requirements

Required Storage Conditions

Prior to Opening the Dry Packing

The following are required storage conditions prior to opening the dry packing:

• Normal temperature: 5~40˚C
• Normal humidity: 80% (Relative humidity) or less
• Storage period: One year or less

After Opening the Dry Packing

The following are required storage conditions after opening the dry packing (to prevent moisture absorption):

• Storage conditions for one-time soldering:

  • Temperature: 5-25°C
  • Humidity: 60% or less
  • Period: 72 hours or less after opening

• Storage conditions for two-time soldering

  • Storage conditions following opening and prior to performing the 1^st reflow:

    • Temperature: 5-25°C
    • Humidity: 60% or less
    • Period: A hours or less after opening

  • Storage conditions following completion of the 1^st reflow and prior to performing the 2^nd reflow

    • Temperature: 5-25°C
    • Humidity: 60% or less
    • Period: B hours or less after completion of the 1st reflow

Temporary Storage Requirements after Opening

The following are temporary storage requirements after opening:

• Only re-store the devices once prior to soldering.
• Use a dry box or place desiccant (with a blue humidity indicator) with the devices and perform dry packing again using vacuumed heat-sealing.

The following indicate the required storage period, temperature, and humidity for this temporary storage:

• Storage temperature and humidity:

  

*** - External atmosphere temperature and humidity of the dry packing

• Storage period:

  • X1+X2 – Refer to Material handling information
  • Required Storage Conditions.  Keep is X1+X2 within 72 hours.
  • Y – Keep within two weeks or less.

Baking Conditions

Baking conditions and processes for the module follow the J-STD-033 standard which includes the following:

• The calculated shelf life in a sealed bag is 12 months at <40℃ and <80% relative humidity.
• Once the packaging is opened, the SiP must be mounted (per MSL4/Moisture Sensitivity Level 4) within 72 hours at <30˚C and <60% relative humidity.

If the SiP is not mounted within 72 hours or if, when the dry pack is opened, the humidity indicator card displays >10% humidity, then the product must be baked for 48 hours at 125 ˚C (±5 ˚C).

Reflow Profile

Reliability Tests

Climatic and Dynamic

Climatic and Dynamic Reliability Test Results for BL54L15/BL54L10 Modules

Reliability Prediction

MTBF Predictions for BL54L15/BL54L10 Modules

Regulatory, Qualification & Certifications

Regulatory Approvals

Full regulatory information on the BL54L15/BL54L10, including the Regulatory Information Guide, grants, and test reports are available on the BL54L15 product page and BL54L10 product page.

The BL54L15/BL54L10 holds current certifications in the following countries:

BL54L15 Certifications

Certified Antennas

Bluetooth SIG Qualification

The Bluetooth Qualification Process promotes global product interoperability and reinforces the strength of the Bluetooth® brand and ecosystem to the benefit of all Bluetooth SIG members. The Bluetooth Qualification Process helps member companies ensure their products that incorporate Bluetooth technology comply with the Bluetooth Patent & Copyright License Agreement and the Bluetooth Trademark License Agreement (collectively, the Bluetooth License Agreement) and Bluetooth Specifications.

The Bluetooth Qualification Process is defined by the Qualification Program Reference Document (QPRD) v3.

To demonstrate that a product complies with the Bluetooth Specification(s), each member must for each of its products:

• Identify the product, the design included in the product, the Bluetooth Specifications that the design implements, and the features of each implemented specification
• Complete the Bluetooth Qualification Process by submitting the required documentation for the product under a user account belonging to your company

The Bluetooth Qualification Process consists of the phases shown below:

To complete the Qualification Process the company developing a Bluetooth End Product shall be a member of the Bluetooth SIG.  To start the application please use the following link: Apply for Adopter Membership

Scope

This guide is intended to provide guidance on the Bluetooth Qualification Process for End Products that reference multiple existing designs, that have not been modified, (refer to Section 3.2.2.1 of the Qualification Program Reference Document v3).

For a Product that includes a new Design created by combining two or more unmodified designs that have DNs or QDIDs into one of the permitted combinations in Table 3.1 of the QPRDv3, a Member must also provide the following information:

• DNs or QDIDs for Designs included in the new Design
• The desired Core Configuration of the new Design (if applicable, see Table 3.1 below)
• The active TCRL Package version used for checking the applicable Core Configuration (including transport compatibility) and evaluating test requirements

Any included Design must not implement any Layers using withdrawn specification(s).

When creating a new Design using Option 2a, the Inter-Layer Dependency (ILD) between Layers included in the Design will be checked based on the latest TCRL Package version used among the included Designs.

For the purposes of this document, it is assumed that the member is combining unmodified Core-Controller Configuration and Core-Host Configuration designs, to complete a Core-Complete Configuration.

Qualification Steps When Referencing multiple existing designs, (unmodified) – Option 2a in the QPRDv3

For this qualification option, follow these steps:

1. To start a listing, go to: https://qualification.bluetooth.com/
2. Select Start the Bluetooth Qualification Process.

3. Product Details to be entered:

   1. Project Name (this can be the product name or the Bluetooth Design name).
   2. Product Description
   3. Model Number
   4. Product Publication Date (the product publication date may not be later than 90 days after submission)
   5. Product Website (optional)
   6. Internal Visibility (this will define if the product will be visible to other users prior to publication)
   7. If you have multiple End Products to list then you can select ‘Import Multiple Products’, firstly downloading and completing the template, then by ‘Upload Product List’.  This will populate Qualification Workspace with all your products.

4. Specify the Design:

   1. Do you include any existing Design(s) in your Product? Answer Yes, I do.
   2. Enter the multiple DNs or QDIDs used in your, (for Option 2a two or more DNs or QDIDs must be referenced)
   3. Select ‘I’m finished entering DN’s
   4. Once the DNs or QDIDs are selected they will appear on the left-hand side, indicating the layers covered by the design (should show Core-Controller and Core Host Layers covered).
   5. What do you want to do next? Answer, ‘Combine unmodified Designs’.
   6. The Qualification Workspace Tool will indicate that a new Design will be created and what type of Core-Complete configuration is selected.
   7. An active TCRL will be selected for the design.
   8. Perform the Consistency Check, which should result in no inconsistencies
   9. If there are any inconsistencies these will need to be resolved before proceeding
   10. Save and go to Test Plan and Documentation

5. Test Plan and Documentation

   1. As no modifications have been made to the combined designs the tool should report the following message:
      ‘No test plan has been generated for your new Design. Test declarations and test reports do not need to be submitted. You can continue to the next step.’
   2. Save and go to Product Qualification fee

6. Product Qualification Fee:

   1. It’s important to make sure a Prepaid Product Qualification fee is available as it is required at this stage to complete the Qualification Process.
   2. Prepaid Product Qualification Fee’s will appear in the available list so select one for the listing.
   3. If one is not available select ‘Pay Product Qualification Fee’, payment can be done immediately via credit card, or you can pay via Invoice.  Payment via credit will release the number immediately, if paying via invoice the number will not be released until the invoice is paid.
   4. Once you have selected the Prepaid Qualification Fee, select ‘Save and go to Submission’

7. Submission:

   1. Some automatic checks occur to ensure all submission requirements are complete.
   2. To complete the listing any errors must be corrected
   3. Once you have confirmed all design information is correct, tick all of the three check boxes and add your name to the signature page.
   4. Now select ‘Complete the Submission’.
   5. You will be asked a final time to confirm you want to proceed with the submission, select ‘Complete the Submission’.
   6. Qualification Workspace will confirm the submission has been submitted.  The Bluetooth SIG will email confirmation once the submission has been accepted, (normally this takes 1 working day).

8. Download Product and Design Details (SDoC):

   1. You can now download a copy of the confirmed listing from the design listing page and save a copy in your Compliance Folder

For further information, please refer to the following webpage:

https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/

Example Design Combinations

The following gives an example of a design possible under option 1:

Ezurio End Product design using Nordic Component based design

Qualify More Products

If you develop further products based on the same design in the future, it is possible to add them free of charge.  The new product must not modify the existing design i.e add ICS functionality, otherwise a new design listing will be required.

To add more products to your design, select ‘Manage Submitted Products’ in the Getting Started page, Actions, Qualify More Products.  The tool will take you through the updating process.

Ordering Information

Legacy - Revision History