Sona IF573 Series

Introduction

Overview

This document describes key hardware aspects of the Ezurio Sona™ IF573 series wireless modules providing either PCIe v3.0 Gen2 or SDIO 3.0 interface for WLAN connection and high-speed 4-wire UART interface for Bluetooth^® connection. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources and includes information found in the Infineon CYW55573MIWBGT data sheet issued on March 23, 2023, along with other documents provided by Infineon.

For full documentation on the Sona IF573, visit:

https://www.ezurio.com/sona-if573

General Description

The Sona IF573 series wireless module is an integrated, small form factor Wi-Fi/Bluetooth module that is optimized for low-power mobile devices, featuring:

• Wi-Fi 6E: Tri-band 2x2 MIMO IEEE 802.11a/b/g/n/ac/ax WLAN
• Bluetooth^® Dual Mode

The integration of all WLAN and Bluetooth functionality in a single package supports low cost and simple implementation along with flexibility for platform-specific customization. It is available in both M.2 2230 E-Key and M.2 1318 solder-down form factor.

This device is pre-calibrated and integrates the complete transmit/receive RF paths including bandpass filter, diplexer, switches, reference crystal oscillator, and power management units (PMU). Both variants support three integrated MHF4 connectors, with two ports for WLAN and one dedicated for Bluetooth. The M.2 1318 solder down module also supports an RF trace pin option for use with external antenna solutions.  For a list of certified antennas see Certified Antennas in the datasheet.

The Sona IF573 series device supports IEEE 802.11ax tri-band (2.4/5/6 GHz) 2x2 MIMO with data rates up to MCS11 (287 Mbps PHY data rate for 2.4 GHz band and 1.2 Gbps PHY data rate for 5/6 GHz). The device has a dedicated Bluetooth port for best Wi-Fi + Bluetooth coexistence performance. The device’s low power consumption, radio architecture and power management unit (PMU) proprietary power save technologies allow for extended battery life.

In addition, its tri-band IEEE 802.11ax and Bluetooth radio includes full digital MAC and baseband engines that handle all 802.11 CCK/OFDM/OFDMA® 2.4/5/6 GHz and Bluetooth Core 6.0 (Basic Rate, Enhanced Data Rate, and Bluetooth Low Energy) baseband and protocol processing.

The Sona IF573 series wireless modules include two product SKUs which have different RF paths. Please contact Ezurio Sales/FAE for further information

This datasheet is subject to change. Please contact Ezurio for further information.

Application Areas

• Medical Devices (Infusion pumps, HD Imaging, Vitals Monitoring, Gateways, Beds, Blood Analyzers)
• Industrial IoT
• Rugged Handheld Devices

Features & Benefits

The Sona IF573 device features and benefits are described in the following table.

Specification Summary

Processor / SoC / Chipset

Wi-Fi

Standards	IEEE 802.11ax, 11ac, 11a/b/g/n, 11d/h, 11i, 11r, 11w, 11e, 11k, 11ai, 11v
Interface	PCIe v3.0 Gen2 Secure Digital I/O 2.0/3.0
Spatial Streams	2 (2x2 MU-MIMO) [802.11ax/ac/n)
Supported Data Rates	Support 802.11 ax/ac/a/b/g/n 2x2 MU-MIMO. 802.11b: (DSSS, CCK) 1, 2, 5.5, 11 Mbps 802.11a/g: (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps 802.11n: (OFDM, HT20/HT40, MCS0-15) 802.11ac: (OFDM, VHT20, MCS0-8; OFDM, VHT40/HT80, MCS0-9) 802.11ax: (2.4 GHz / OFDM / HE20 / MCS0-11; 2.4 GHz / OFDMA / HE20 / MCS0-11) 802.11ax: (5 GHz, 6 GHz / OFDM / HE20, HE40, HE80 / MCS0-11; 5 GHz, 6 GHz / OFDMA / HE20, HE40, HE80 / MCS0-11)
Modulation Schemes	BPSK, QPSK, CCK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM
Network Architecture Type	Infrastructure (client operation)
Wi-Fi Media	Direct Sequence-Spread Spectrum (DSSS) Complementary Code Keying (CCK) Orthogonal Frequency Division Multiplexing (OFDM) Orthogonal Frequency Division Multiple Access (OFDMA)
Wi-Fi Multimedia	WMM Wi-Fi Multimedia - PowerSave (WMM-PS with U-APSD) WMM-Sequential Access (WMM-SA)

Bluetooth

Radio Performance

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Functional Descriptions

WLAN Functional Description

The Sona IF573 series wireless module is designed based on the Infineon AIROC CYW55573MIWBGT Wi-Fi 6E chipset (dual-core 2x2 MIMO). It is optimized for high speed, reliability, and low-power embedded applications. It is integrated with tri-band WLAN (2.4/5/6 GHz) and Bluetooth Core 6.0. Its functionality is listed below.

Bluetooth Functional Description

The Sona IF573 series wireless module includes a fully integrated Bluetooth baseband/radio. Several features and functions are listed below.

Power-Up Sequence and Timing

Sona IF573 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator block.

Boot Mode

Description of Control Signals

• WL_REG_ON: Used to power up the WLAN. When this pin is high, the internal regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset.  This signal is connected to the W_DISABLE1# pin on the M.2 interface.
• BT_REG_ON: Used to power up the Bluetooth section. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the Bluetooth section is in reset.  This signal is connected to the W_DISABLE2# pin on the M.2 interface.
• M.2 1318 - VBAT and VDDIO should not rise 10% - 90% faster than 40 microseconds.
• M.2 1318 - VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Control Signal Timing Diagrams

Hardware Architecture

Block Diagrams

M.2 1318 Solder-down

M.2 2230 E-Key

Pin-Out

M.2 1318 Solder-down

M.2 2230 E-Key

Package Layout

Mechanical Drawings

M.2 1318

Module dimensions of Sona IF573 M.2 1318 package is 18 x 13 x 1.9 mm. Detailed drawings are shown below.

M.2 2230 E-Key

Module dimensions of Sona IF573 M.2 2230 E-Key module is 22 x 30 x 2.7 mm. Detailed drawings are shown below.

M.2 2230 E-Key Mounting

The Sona IF573 M.2 2230 E-Key module connects to the host via a standard PCI EXPRESS M2 connector.

Kyocera’s 6411 series provides 1.8mm, 2.3mm and 3.2mm connector heights. JAE’s SM3 series provides 1.2mm, 2.15mm, 3.1mm and 4.1mm connector heights. 

The Sona IF573 M.2 2230 E-Key module is a single-sided component module so we recommend the connectors listed below.

The corresponding standoffs are listed below.

Host Interface Specifications

SDIO Specifications

The Sona IF573 series wireless module SDIO host interface pins are powered from the VDDIO voltage supply, which is set internally at 1.8V on the M.2 module. The SDIO electrical specifications are identical for the 1-bit SDIO and 4-bit SDIO modes. 

Default Speed, High-Speed Modes

SDIO timing requirements

SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

SDIO timing requirements - SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)

SDR104 Mode (208 MHz) (1.8V)

SDIO timing requirements -  SDR104 mode (up to 208MHz) (1.8V)

PCI Express Specifications

The Sona IF573 series wireless module supports the PCIe interface, which provides high-performance serial I/O interconnects and is also protocol compliant and electrically compatible with the PCI Express Base Specification v3.0 running at Gen2 speeds.

Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 7. A configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and reception of System Management Messages by communicating with PCIe layers.

Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and Sona IF573 device. The transmit side processes outbound packets whereas the receive side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to indicate the packet type and any other optional fields.

PCM Specifications

PCM Interface

The Sona IF573 series wireless module supports a PCM interface. The PCM interface on the Sona IF573 series wireless module can connect to linear PCM codec devices in Master/Slave mode. In Master mode, the Sona IF573 generates the BT_PCM_CLK and BT_PCM_SYNC signals, and in Slave mode, these signals are provided by another master on the PCM interface and are input to the Sona IF573 module.

The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

PCM Interface Timing

PCM timing specification – Short Frames Sync, Master Mode

PCM timing specification – Short Frame Sync, Slave Mode

PCM timing specification – Long Frame Sync, Master Mode

PCM timing specification – Long Frame Sync, Slave Mode

PCM timing specification – Short Frame Sync, Receive Only, Burst Mode

PCM timing specification – Long Frame Sync, Receive Only, Burst Mode

JTAG Specifications

The Sona IF573 supports the JTAG interface for use with proprietary debug and characterization test tools during board bring-up.

Electrical Characteristics

Absolute Maximum Ratings

The following table summarizes the absolute maximum ratings for the Sona IF573 series wireless module. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended.

Recommended Operating Conditions

The following table lists the recommended operating conditions for the Sona IF573 series wireless module.

DC Electrical Characteristics

The following table lists the general DC electrical characteristics over recommended operating conditions (unless otherwise specified).

Radio Characteristics

WLAN Radio Receiver Characteristics

The following tables summarize the Sona IF573 series wireless module receiver characteristics.

WLAN receiver characteristics for 2.4 GHz single chain operation

WLAN receiver characteristics for 5 GHz single chain operation

WLAN receiver characteristics for 6 GHz single chain operation

WLAN Transmitter Characteristics

The following tables summarize the Sona IF573 series wireless module transmitter characteristics.

WLAN transmitter characteristics for 2.4 GHz operation (VBAT = 3.3V, VDDIO = 1.8V)

WLAN transmitter characteristics for 5 GHz operation (VBAT=3.3V, VDDIO=1.8V)

WLAN transmitter characteristics for UNII-5 and UNII-6 operation (VBAT = 3.3V, VDDIO = 1.8V)

WLAN transmitter characteristics for UNII-7 and UNII-8 operation (VBAT = 3.3V, VDDIO = 1.8V)

WLAN Current Consumption

The following tables summarize the Sona IF573 series wireless module current consumption.

WLAN current consumption on 2.4 GHz (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

WLAN current consumption on 5 GHz (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

WLAN current consumption on UNII-5 band (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

WLAN current consumption on UNII-6 band (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

WLAN current consumption on UNII-7 band (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

WLAN current consumption on UNII-8 band (VBAT = 3.3V, VDDIO = 1.8V, BT_REG_ON = Low)

Bluetooth Receiver Characteristics

The following tables describe the performance of the Bluetooth receiver at 25°C.

Basic Rate receiver performance (VBAT = 3.3V, VDDIO = 1.8V)

Enhanced Data Rate receiver performance (VBAT = 3.3V, VDDIO = 1.8V)

Bluetooth Transmitter Characteristics

The following tables describe the performance of the Bluetooth transmitter at 25°C.

BR / EDR transmitter performance (VBAT = 3.3V, VDDIO = 1.8V)

Bluetooth Current Consumption

The following tables describe the Bluetooth current consumption at 25°C.

Bluetooth transmitter current consumption (VBAT = 3.3V, VDDIO = 1.8V, WL_REG_ON = OFF)

BLE RF Specifications

BLE RF Specifications (VBAT = 3.3V, VDDIO = 1.8V)

Integration Guidelines

Antenna Characteristics

Circuit (Overview and Checklist)

The following is a list of RF layout design guidelines and recommendation when installing a Ezurio radio into your device.

• Do not run antenna cables directly above or directly below the radio.

• Do not place any parts or run any high-speed digital lines below the radio.

• Ensure that there is the maximum allowable spacing separating the antenna connectors on the Ezurio radio from the antenna. In addition, do not place antennas directly above or directly below the radio.

• Ezurio recommends the use of a double-shielded cable for the connection between the radio and the antenna elements.

• Be sure to put a 10uF/16V/0603 capacitor on EACH 3.3V power pin. Place the capacitor as close as possible to the pin to ensure correct PMU operation.

• Use proper electro-static-discharge (ESD) procedures when installing the Ezurio radio module. To avoid negatively impacting Tx power and receiver sensitivity, do not cover the antennas with metallic objects or components.

External Antenna Integration

RF Antenna Connector Configuration

Antenna connectors for the SMT and M.2 2230 modules are designated as shown below.

Host Platform Implementation Details

M.2 1318 WLAN Interface Selection

The Sona IF573 M.2 1318 module must be configured for either PCIe or SDIO WLAN interface.  Configuration is done with resistor strapping as specified below.

Bluetooth Interface Requirements

The CYW55573 Bluetooth CPU core requires the UART_CTS input to be held low at the point the BT_REG_ON (W_DISABLE2#) signal goes high to enable secure firmware download.  In addition, the HCI interface uses the standard H4 protocol which requires four-wire hardware handshaking. 

This requires that the host implement GPIO control over BT_REG_ON/W_DISABLE2# and implement full RTS/CTS handshaking.

Low Power Clock

The Sona IF573 requires a 32KHz clock on the SUSCLK input.  This clock drives various internal state machines and must be provided by the host even if low power operation is not needed.

WL_DEV_WAKE Mapping

The WL_DEV_WAKE feature is mapped to different pins on the M.2 1318 module depending on the WLAN interface selection. See below for details.

32 KHz Crystal

Application Note for Surface Mount Modules

Introduction

Ezurio’s surface mount modules are designed to conform to all major manufacturing guidelines. This application note is intended to provide additional guidance beyond the information that is presented in the user manual. This application note is considered a living document and will be updated as new information is presented.

The modules are designed to meet the needs of several commercial and industrial applications. They are easy to manufacture and conform to current automated manufacturing processes.

Recommended Stencil Aperture

Reflow Parameters

Convection reflow or IR/Convection reflow (one-time soldering or two-time soldering in air or nitrogen environment)

Measuring point – IC package surface

Temperature profile:

• Solder paste alloy: SAC305(Sn96.5 / Ag3.0 / Cu 0.5)
• Pre-heat temperature: 150℃ ~ 200℃; Soak time: 60 second ~ 120 second
• Peak temperature: 235℃ ~ 250℃
• Time above 220℃: 40 second ~ 90 second
• Optimal cooling rate < 3℃/second
• The oxygen concentration < 2000 ppm

Baking Conditions

Baking Conditions

Baking conditions and processes for the module follow the J-STD-033 standard which includes the following:

• The calculated shelf life in a sealed bag is 12 months at <40℃ and <80% relative humidity.
• Once the packaging is opened, the SiP must be mounted (per MSL4/Moisture Sensitivity Level 4) within 72 hours at <30˚C and <60% relative humidity.

If the SiP is not mounted within 72 hours or if, when the dry pack is opened, the humidity indicator card displays >10% humidity, then the product must be baked for 48 hours at 125 ˚C (±5 ˚C).

Cautions when Removing the M.2 1318 from the Platform for RMA

• Bake the platform before removing the M.2 1318 module from the platform.
• Remove the M.2 1318 module by using a hot air gun. This process should be carried out by a skilled technician.

Recommended conditions:

• One-side component platform:

  • Set the hot plate at 280°C.
  • Put the platform on the hot plate for 8~10 seconds.

  • Remove the device from platform.
    

    

• Two-side components platform:

  • Use two hot air guns.
  • On the bottom, use a pre-heated nozzle (temp setting of 200~250°C) at a suitable distance from the platform PCB.

  • On the top, apply a remove nozzle (temp setting of 330°C). Heat until device can be removed from platform PCB.
    

    
• Remove the residue solder under the bottom side of device. (Note: Alternate module pictured as an example)

(Not accepted for RMA)	(Accepted for RMA analysis)
Example module with residue solder on the bottom	Example module without residue solder

Remove and clean the residue flux as needed.

Precautions for Use

• Opening/handling/removing must be done on an anti-ESD treated workbench. All workers must also have undergone anti-ESD treatment.
• The devices should be mounted within one year of the date of delivery.
• The Sona IF573 modules are MSL level 4 rated.

Shipping and Labeling

Packaging

M.2 1218 Solder-Down

There are 1,000 Sona IF573 modules taped in a reel (and packaged in a pizza box) and three boxes per carton (3,000 modules per carton). Reel, boxes, and carton are labeled with the appropriate labels. See below for more information.

M.2 2230 E-Key Module

Labeling

M.2 1218 Solder-Down

The following labels are located on the antistatic bag.

The following label is located on the pizza box.

The following package label is located on adjacent sides of the master carton.

M.2 2230 E-Key Module

The following label is placed on the bag and the inner box.  

The following label is located on the adjacent sides of the master carton.  

Environmental and Reliability

Environmental Requirements

Required Storage Conditions

Prior to Opening the Dry Packing

The following are required storage conditions prior to opening the dry packing:

• Normal temperature: 5~40˚C
• Normal humidity: 80% (Relative humidity) or less
• Storage period: One year or less

After Opening the Dry Packing

The following are required storage conditions after opening the dry packing (to prevent moisture absorption):

• Storage conditions for one-time soldering:

  • Temperature: 5-25°C
  • Humidity: 60% or less
  • Period: 72 hours or less after opening

• Storage conditions for two-time soldering

  • Storage conditions following opening and prior to performing the 1^st reflow:

    • Temperature: 5-25°C
    • Humidity: 60% or less
    • Period: A hours or less after opening

  • Storage conditions following completion of the 1^st reflow and prior to performing the 2^nd reflow

    • Temperature: 5-25°C
    • Humidity: 60% or less
    • Period: B hours or less after completion of the 1^st reflow

Temporary Storage Requirements after Opening

The following are temporary storage requirements after opening:

• Only re-store the devices once prior to soldering.
• Use a dry box or place desiccant (with a blue humidity indicator) with the devices and perform dry packing again using vacuumed heat-sealing.

The following indicate the required storage period, temperature, and humidity for this temporary storage:

• Storage temperature and humidity:
  

  

  *** - External atmosphere temperature and humidity of the dry packing

• Storage period:

  • X1+X2 – Refer to Required Storage Conditions.  Keep is X1+X2 within 72 hours.
  • Y – Keep within two weeks or less.

Reliability Tests

The Sona IF573 modules were tested for reliability. Test items and the corresponding standards are shown below.

Environmental and Mechanical

The following are the followed reliability test procedures.

Sona IF573 M.2 1318 Solder-down Module Reliability Test Items and Standards

Sona IF573 M.2 2230 E-Key Module Reliability Test Item and Standards

Reliability Prediction

Regulatory, Qualification & Certifications

Regulatory Approvals

The Sona IF573 holds current certifications in the following countries:

Certified Antennas

The Sona IF573 module was tested with antennas listed in the following table. The OEM can choose a different manufacturer’s antenna but must make sure it is of same type and that the gain is lesser than or equal to the antenna that is approved for use.

Bluetooth SIG Qualification

The Bluetooth Qualification Process promotes global product interoperability and reinforces the strength of the Bluetooth® brand and ecosystem to the benefit of all Bluetooth SIG members. The Bluetooth Qualification Process helps member companies ensure their products that incorporate Bluetooth technology comply with the Bluetooth Patent & Copyright License Agreement and the Bluetooth Trademark License Agreement (collectively, the Bluetooth License Agreement) and Bluetooth Specifications.

The Bluetooth Qualification Process is defined by the Qualification Program Reference Document (QPRD) v3.

To demonstrate that a product complies with the Bluetooth Specification(s), each member must for each of its products:

• Identify the product, the design included in the product, the Bluetooth Specifications that the design implements, and the features of each implemented specification
• Complete the Bluetooth Qualification Process by submitting the required documentation for the product under a user account belonging to your company

The Bluetooth Qualification Process consists of the phases shown below:

To complete the Qualification Process the company developing a Bluetooth End Product shall be a member of the Bluetooth SIG.  To start the application please use the following link: Apply for Adopter Membership

Scope

This guide is intended to provide guidance on the Bluetooth Qualification Process for End Products that reference multiple existing designs, that have not been modified, (refer to Section 3.2.2.1 of the Qualification Program Reference Document v3).

For a Product that includes a new Design created by combining two or more unmodified designs that have DNs or QDIDs into one of the permitted combinations in Table 3.1 of the QPRDv3, a Member must also provide the following information:

• DNs or QDIDs for Designs included in the new Design
• The desired Core Configuration of the new Design (if applicable, see Table 3.1 below)
• The active TCRL Package version used for checking the applicable Core Configuration (including transport compatibility) and evaluating test requirements

Any included Design must not implement any Layers using withdrawn specification(s).

When creating a new Design using Option 2a, the Inter-Layer Dependency (ILD) between Layers included in the Design will be checked based on the latest TCRL Package version used among the included Designs.

For the purposes of this document, it is assumed that the member is combining unmodified Core-Controller Configuration and Core-Host Configuration designs, to complete a Core-Complete Configuration.

Qualification Steps When Referencing multiple existing designs, (unmodified) – Option 2a in the QPRDv3

For this qualification option, follow these steps:

1. To start a listing, go to: https://qualification.bluetooth.com/
2. Select Start the Bluetooth Qualification Process.

3. Product Details to be entered:

   1. Project Name (this can be the product name or the Bluetooth Design name).
   2. Product Description
   3. Model Number
   4. Product Publication Date (the product publication date may not be later than 90 days after submission)
   5. Product Website (optional)
   6. Internal Visibility (this will define if the product will be visible to other users prior to publication)
   7. If you have multiple End Products to list then you can select ‘Import Multiple Products’, firstly downloading and completing the template, then by ‘Upload Product List’.  This will populate Qualification Workspace with all your products.

4. Specify the Design:

   1. Do you include any existing Design(s) in your Product? Answer Yes, I do.
   2. Enter the multiple DNs or QDIDs used in your, (for Option 2a two or more DNs or QDIDs must be referenced)
   3. Select ‘I’m finished entering DN’s
   4. Once the DNs or QDIDs are selected they will appear on the left-hand side, indicating the layers covered by the design (should show Core-Controller and Core Host Layers covered).
   5. What do you want to do next? Answer, ‘Combine unmodified Designs’.
   6. The Qualification Workspace Tool will indicate that a new Design will be created and what type of Core-Complete configuration is selected.
   7. An active TCRL will be selected for the design.
   8. Perform the Consistency Check, which should result in no inconsistencies
   9. If there are any inconsistencies these will need to be resolved before proceeding
   10. Save and go to Test Plan and Documentation

5. Test Plan and Documentation

   1. As no modifications have been made to the combined designs the tool should report the following message:
      ‘No test plan has been generated for your new Design. Test declarations and test reports do not need to be submitted. You can continue to the next step.’
   2. Save and go to Product Qualification fee

6. Product Qualification Fee:

   1. It’s important to make sure a Prepaid Product Qualification fee is available as it is required at this stage to complete the Qualification Process.
   2. Prepaid Product Qualification Fee’s will appear in the available list so select one for the listing.
   3. If one is not available select ‘Pay Product Qualification Fee’, payment can be done immediately via credit card, or you can pay via Invoice.  Payment via credit will release the number immediately, if paying via invoice the number will not be released until the invoice is paid.
   4. Once you have selected the Prepaid Qualification Fee, select ‘Save and go to Submission’

7. Submission:

   1. Some automatic checks occur to ensure all submission requirements are complete.
   2. To complete the listing any errors must be corrected
   3. Once you have confirmed all design information is correct, tick all of the three check boxes and add your name to the signature page.
   4. Now select ‘Complete the Submission’.
   5. You will be asked a final time to confirm you want to proceed with the submission, select ‘Complete the Submission’.
   6. Qualification Workspace will confirm the submission has been submitted.  The Bluetooth SIG will email confirmation once the submission has been accepted, (normally this takes 1 working day).

8. Download Product and Design Details (SDoC):

   1. You can now download a copy of the confirmed listing from the design listing page and save a copy in your Compliance Folder

For further information, please refer to the following webpage:

https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/

Example Design Combinations

The following gives an example of a design possible under option 2a:

Ezurio Controller Subsystem + BlueZ 5.50 Host Stack (Ezurio Sona IF573 based design)

Qualify More Products

If you develop further products based on the same design in the future, it is possible to add them free of charge.  The new product must not modify the existing design i.e add ICS functionality, otherwise a new design listing will be required.

To add more products to your design, select ‘Manage Submitted Products’ in the Getting Started page, Actions, Qualify More Products.  The tool will take you through the updating process.

Ordering Information

Legacy - Revision History